ST STM32L4x6 Reference Manual page 609

RM0351
Internal clock sources - see SPICKSEL[1:0] in DFSDM_CHCFGyR1 register:
•
DFSDM_CKOUT signal:
–
–
•
DFSDM_CKOUT/2 signal (generated on DFSDM_CKOUT rising edge):
–
–
•
DFSDM_CKOUT/2 signal (generated on DFSDM_CKOUT falling edge):
–
–
Note: An internal clock source can only be used when the external Σ∆ modulator uses
DFSDM_CKOUT signal as a clock input (to have synchronous clock and data operation).
Internal clock source usage can save DFSDM_CKINy pin connection (DFSDM_CKINy pins
can be used for other purpose).
The clock source signal frequency must be in the range 0 - 20 MHz for SPI coding and less
than f
DFSDMCLK
Manchester coded data input format operation
In Manchester coded format, the data stream is sent in serial format through
DFSDM_DATINy pin only. Decoded data and clock signal are recovered from serial stream
after Manchester decoding. There are two possible settings of Manchester codings (see
SITP[1:0] bits in DFSDM_CHCFGyR1 register):
•
signal rising edge = log 0; signal falling edge = log 1
•
signal rising edge = log 1; signal falling edge = log 0
The recovered clock signal frequency for Manchester coding must be in the range
0 - 10 MHz and less than f
To correctly receive Manchester coded data, the CKOUTDIV divider (in
DFSDM_CHCFG0R1 register) must be set with respect to expected Manchester data rate
according formula:
For connection to external Σ∆ modulator which uses directly its clock input (from
DFSDM_CKOUT) to generate its output serial communication clock.
Sampling point: on rising/falling edge according SITP[1:0] setting.
For connection to external Σ∆ modulator which divides its clock input (from
DFSDM_CKOUT) by 2 to generate its output serial communication clock (and this
output clock change is active on each clock input rising edge).
Sampling point: on each second DFSDM_CKOUT falling edge.
For connection to external Σ∆ modulator which divides its clock input (from
DFSDM_CKOUT) by 2 to generate its output serial communication clock (and this
output clock change is active on each clock input falling edge).
Sampling point: on each second DFSDM_CKOUT rising edge.
/4.
DFSDMCLK
( ( ) ×
CKOUTDIV 1 T
+
SYSCLK
DocID024597 Rev 3
Digital filter for sigma delta modulators (DFSDM)
/6.
) T < < (
2
Manchester clock
× ×
CKOUTDIV T
SYSCLK
)
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