ST STM32L4x6 Reference Manual page 977

RM0351
Bit 5 CC2P: Capture/Compare 2 output polarity
Refer to CC1P description
Bit 4 CC2E: Capture/Compare 2 output enable
Refer to CC1E description
Bit 3 CC1NP: Capture/Compare 1 complementary output polarity
CC1 channel configured as output:
CC1 channel configured as input:
Note: 1.This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK
Bit 2 CC1NE: Capture/Compare 1 complementary output enable
Bit 1 CC1P: Capture/Compare 1 output polarity
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input: The CC1NP/CC1P bits select the polarity of TI1FP1 and
TI2FP1 for trigger or capture operations.
Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK
0: OC1N active high
1: OC1N active low
This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer
to CC1P description.
bits in TIMx_BDTR register) and CC1S="00" (the channel is configured in output).
2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit
is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the
preloaded bit only when a Commutation event is generated.
0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N
and CC1E bits.
1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI,
OSSR, OIS1, OIS1N and CC1E bits.
00: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger
operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation
in gated mode).
01: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger
operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in
gated mode).
10: reserved, do not use this configuration.
11: non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges
(capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted
(trigger operation in gated mode).
bits in TIMx_BDTR register).
2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit
is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the
preloaded bit only when a Commutation event is generated.
General-purpose timers (TIM15/16/17)
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