Aes Key Register 2 (Aes_Keyr2) (Key [95:64]) - ST STM32L4x6 Reference Manual

Advanced encryption standard hardware accelerator (AES)
25.14.7

AES key register 2 (AES_KEYR2) (key [95:64])

Address offset: 0x18
Reset value: 0x0000 0000
31 30 29 28
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15 14 13 12
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Bits 31:0 KEYR2[31:0]: Data output register (key [95:64])
Refer to the description of AES_KEYR0.
25.14.8 AES key register 3 (AES_KEYR3) (MSB: key[127:96])
Address offset: 0x1C
Reset value: 0x0000 0000
31 30 29 28
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15 14 13 12
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Bits 31:0 KEYR3[31:0]: Data output register (MSB key [127:96])
Refer to the description of AES_KEYR0.
25.14.9 AES initialization vector register 0 (AES_IVR0) (LSB: IVR[31:0])
Address offset: 0x20
Reset value: 0x0000 0000
31 30 29 28
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15 14 13 12
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744/1693
27 26 25 24
KEYR2[31:16]
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11 10 9 8
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27 26 25 24
KEYR3[31:16]
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11 10 9 8
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27 26 25 24
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11 10 9 8
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DocID024597 Rev 3
23 22 21
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7 6 5
KEYR2[15:0]
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23 22 21
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7 6 5
KEYR3[15:0]
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23 22 21
IVR0[31:16]
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7 6 5
IVR0[15:0]
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20 19 18 17
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4 3 2 1
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20 19 18 17
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4 3 2 1
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20 19 18 17
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4 3 2 1
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RM0351
16
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0
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16
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0
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16
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0
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