Table 120. Dfsdm External Pins; Table 121. Dfsdm Internal Signals; Table 122. Dfsdm Triggers Connection; Dfsdm Pins And Internal Signals - ST STM32L4x6 Reference Manual

Digital filter for sigma delta modulators (DFSDM)
Note: This example shows 4 DFSDM interfaces and 8 input channels (max. configuration).
21.3.2

DFSDM pins and internal signals

Name
VDD
VSS
DFSDM_CKIN[7:0]
DFSDM_DATIN[7:0]
DFSDM_CKOUT
DFSDM_EXTRG[1:0]
DFSDM_INTRG[8:0]
DFSDM_BREAK[3:0]
DFSDM_DMAREQ[3:0]
DFSDM_INT[3:0]
DFSDM_INTRG[0]
DFSDM_INTRG[1]
DFSDM_INTRG[2]
DFSDM_INTRG[3]
DFSDM_INTRG[4]
DFSDM_INTRG[5]
DFSDM_INTRG[6]
DFSDM_INTRG[7]
DFSDM_INTRG[8]
DFSDM_EXTRG[0]
DFSDM_EXTRG[1]
606/1693

Table 120. DFSDM external pins

Signal Type
Power supply
Power supply
Clock input
Data input
Clock output
External trigger
signal

Table 121. DFSDM internal signals

Name Signal Type
Internal trigger
signal
break signal
output
DMA request
signal
Interrupt
request signal

Table 122. DFSDM triggers connection

Trigger name
DocID024597 Rev 3
Digital power supply 1.65 - 3.6V.
Digital ground power supply.
Clock signal provided from external Σ∆ modulator. FT input.
Data signal provided from external Σ∆ modulator. FT input.
Clock output to provide clock signal into external Σ∆
modulator.
Input trigger from two EXTI signals to start analog
conversion (from GPIOs: EXTI11, EXTI15).
Input trigger from internal trigger sources to start analog
conversion, see Table 122
Break signals event generation from Analog watchdog or
short-circuit detector
DMA request signal from each DFSDMx (x=0..3): end of
injected conversion event.
Interrupt signal for each DFSDMx (x=0..3)
TIM1_TRGO
TIM1_TRGO2
TIM8_TRGO
TIM8_TRGO2
TIM3_TRGO
TIM4_TRGO
TIM16_OC1
TIM6_TRGO
TIM7_TRGO
EXTI11
EXTI15
Remarks
Remarks
for details.
Trigger source
RM0351