Write Protection (Wrp) - ST STM32L4x6 Reference Manual

Embedded Flash memory (FLASH)
to Changing the Read protection
PCROP1/2_END are also not erased.
Note: It is recommended to align PCROP area with page granularity when using PCROP_RDP, or
to leave free the rest of the page where PCROP zone starts or ends.
3.5.3

Write protection (WRP)

The user area in Flash memory can be protected against unwanted write operations. Two
write-protected (WRP) areas can be defined in each bank, with page (2 KBytes) granularity.
Each area is defined by a start page offset and an end page offset related to the physical
Flash bank base address. These offsets are defined in the WRP address registers:
Bank 1 WRP area A address register
address register
(FLASH_WRP2AR),
The Bank "x" WRP "y" area (x=1,2 and y=A,B) is defined from the address: Bank "x" Base
address + [WRPxy_STRT x 0x800] (included) to the address: Bank "x" Base address +
[(WRPxy_END+1) x 0x800] (excluded).
For example, to protect by WRP from the address 0x08062800 (included) to the address
0x080707FF (included):
•
if boot in flash is done in Bank 1, FLASH_WRP1AR register must be programmed with:
–
–
WRP1B_STRT and WRP1B_END in FLASH_WRP1BR can be used instead (area "B"
in Bank 1).
•
If the two banks are swapped, the protection must apply to bank 2, and
FLASH_WRP2AR register must be programmed with:
–
–
WRP2B_STRT and WRP2B_END in FLASH_WRP2BR can be used instead (area "B
in Bank 2).
When WRP is active, it cannot be erased or programmed. Consequently, a software mass
erase cannot be performed if one area is write-protected.
If an erase/program operation to a write-protected part of the Flash memory is attempted,
the write protection error flag (WRPERR) is set in the FLASH_SR register. This flag is also
set for any write access to:
–
–
–
Note: When the memory read protection level is selected (RDP level = 1), it is not possible to
program or erase Flash memory if the CPU debug features are connected (JTAG or single
wire) or boot code is being executed from RAM or System flash, even if WRP is not
activated.
Note: To validate the WRP options, the option bytes must be reloaded through the OBL_LAUNCH
bit in Flash control register.
104/1693
(FLASH_WRP1BR),
Flash Bank 2 WRP area B address register
WRP1A_STRT = 0xC5.
WRP1A_END = 0xE0.
WRP2A_STRT = 0xC5.
WRP2A_END = 0xE0.
OTP area
part of the Flash memory that can never be written like the ICP
PCROP area.
DocID024597 Rev 3
level). In this case, PCROP1/2_STRT and
(FLASH_WRP1AR),
Flash Bank 2 WRP area A address register
Flash Bank 1 WRP area B
(FLASH_WRP2BR).
RM0351
Flash