Adc Control Register (Adcx_Cr) - ST STM32L4x6 Reference Manual

RM0351
16.5.3

ADC control register (ADCx_CR)

Address offset: 0x08
Reset value: 0x2000 0000
31 30 29
AD
ADCA DEEP ADVREG
LDIF PWD
CAL
rs rw rw
15 14 13
Res. Res. Res. Res.
Bit 31 ADCAL: ADC calibration
This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF to
determine if this calibration applies for single-ended or differential inputs mode.
It is cleared by hardware after calibration is complete.
0: Calibration complete
1: Write 1 to calibrate the ADC. Read at 1 means that a calibration in progress.
Note: Software is allowed to launch a calibration by setting ADCAL only when ADEN=0.
Note: Software is allowed to update the calibration factor by writing ADCx_CALFACT only when
ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is ongoing)
Bit 30 ADCALDIF: Differential mode for calibration
This bit is set and cleared by software to configure the single-ended or differential inputs mode for
the calibration.
0: Writing ADCAL will launch a calibration in Single-ended inputs Mode.
1: Writing ADCAL will launch a calibration in Differential inputs Mode.
Note: Software is allowed to write this bit only when the ADC is disabled and is not calibrating
(ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bit 29 DEEPPWD: Deep-power-down enable
This bit is set and cleared by software to put the ADC in deep-power-down mode.
0: ADC not in deep-power down
1: ADC in deep-power-down (default reset state)
Note: Software is allowed to write this bit only when the ADC is disabled (ADCAL=0, JADSTART=0,
JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bit 28 ADVREGEN: ADC voltage regulator enable
This bits is set by software to enable the ADC voltage regulator.
Before performing any operation such as launching a calibration or enabling the ADC, the ADC
voltage regulator must first be enabled and the software must wait for the regulator start-up time.
0: ADC Voltage regulator disabled
1: ADC Voltage regulator enabled.
For more details about the ADC voltage regulator enable and disable sequences, refer to
Section 16.3.6: ADC Deep-Power-Down Mode (DEEPPWD) & ADC Voltage Regulator
(ADVREGEN).
The software can program this bit field only when the ADC is disabled (ADCAL=0, JADSTART=0,
ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bits 27:6 Reserved, must be kept at reset value.
28 27 26 25
Res. Res. Res.
EN
rw
12 11 10 9
Res. Res. Res.
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
DocID024597 Rev 3
Analog-to-digital converters (ADC)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
JAD AD JAD AD
STP STP START START
rs rs rs rs
17 16
Res. Res.
1 0
AD AD
DIS EN
rs rs
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