ST STM32L0x3 Manuals
Manuals and User Guides for ST STM32L0x3. We have 1 ST STM32L0x3 manual available for free PDF download: Reference Manual
ST STM32L0x3 Reference Manual (1043 pages)
Ultra-low-power advanced Arm-based 32-bit MCUs
Brand: ST
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Category: Microcontrollers
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Size: 12 MB
Table of Contents
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Glossary53
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S1: DMA-Bus57
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Busmatrix57
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Introduction58
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Introduction66
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NVM Interrupts102
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Hard Fault103
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Read103
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Write/Erase103
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Power-Down105
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Read Registers106
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Option Bytes121
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Introduction123
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CRC Operation124
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CRC Registers126
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CRC Register Map129
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Firewall (FW)130
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Introduction130
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Write Protection132
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Code Segment132
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Firewall States135
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Power Supplies142
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Range 1145
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Range 2 and 3146
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Below 1.71 V147
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Low-Power Modes153
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Sleep Mode157
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Stop Mode160
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Standby Mode163
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Debug Mode164
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And Comparators164
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PWR Register Map172
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Reset173
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System Reset173
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Software Reset173
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Power Reset174
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Clocks175
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HSE Clock178
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HSI16 Clock179
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Calibration179
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MSI Clock180
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Calibration180
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HSI48 Clock180
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Pll181
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LSE Clock182
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LSI Clock182
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LSI Measurement182
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Watchdog Clock185
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Frequencies185
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RCC Registers187
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RCC Register Map223
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Introduction226
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RELOAD Value229
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FELIM Value230
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CRS Interrupts230
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CRS Registers231
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CRS Register Map236
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Introduction237
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GPIO Registers246
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Introduction255
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SYSCFG Registers256
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(Syscfg_Exticr1)261
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(Syscfg_Exticr2)262
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(Syscfg_Exticr3)262
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(Syscfg_Exticr4)263
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Introduction265
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Dma266
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DMA Controller266
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DMA Transfers269
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DMA Arbitration270
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DMA Channels271
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DMA Interrupts276
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DMA Registers276
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DMA Register Map286
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Main Features289
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Introduction292
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EXTI Registers297
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Introduction302
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Low Frequency310
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ADC Connectivity311
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Timings315
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Data Management321
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Adc_Tr)326
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Oversampler330
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Analog Watchdog332
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Triggered Mode332
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Main Features334
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Dda335
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ADC Interrupts336
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ADC Registers337
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ADC Register Map351
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Introduction353
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DAC Data Format355
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DAC Data Format358
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Noise Generation362
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DMA Request364
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DMA Underrun364
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DAC Registers365
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(Dac_Dhr12R1)369
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(Dac_Dhr12L1)370
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(Dac_Dhr8R1)370
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(Dac_Dhr12R2)370
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(Dac_Dhr12L2)371
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(Dac_Dhr8R2)371
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(Dac_Dhr12Rd)372
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(Dac_Dhr12Ld)372
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(Dac_Dhr8Rd)372
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Introduction377
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Power Mode379
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COMP Interrupts379
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COMP Registers379
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Introduction384
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Glossary384
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Common Driver388
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COM Signal Bias388
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COM Signal Duty389
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To 1 Mux391
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Segment Driver391
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Blink395
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Deadtime398
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Flowchart404
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LCD Interrupts405
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LCD Registers406
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LCD Register Map412
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Introduction414
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Reset and Clocks417
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Max Count Error419
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Acquisition Mode421
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TSC Interrupts422
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TSC Registers423
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TSC Register Map431
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Introduction433
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Overview435
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Chaining Modes435
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Introduction438
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Data Append439
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Overview443
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Overview448
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Data Swapping451
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Data Padding453
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AES Interrupts456
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AES Registers458
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AES Register Map465
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Introduction467
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Noise Source470
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Post Processing470
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Output Buffer470
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Health Checks471
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RNG Operation471
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RNG Clocking472
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Error Management472
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RNG Interrupts473
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Introduction474
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Data Collection474
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RNG Registers475
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RNG Register Map478
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Time-Base Unit481
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Counter Modes483
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Upcounting Mode483
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Is Not Used489
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Clock Selection493
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PWM Input Mode501
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PWM Mode503
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One-Pulse Mode507
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Debug Mode522
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Introduction547
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Timebase Unit549
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Counter Modes551
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Upcounting Mode551
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Preloaded)554
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Preloaded)555
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Clock Selection562
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PWM Input Mode569
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PWM Mode571
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One-Pulse Mode575
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Debug Mode582
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Introduction602
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Time-Base Unit603
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Counting Mode605
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Preloaded)607
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Clock Source608
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Preloaded)608
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Debug Mode609
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TIM6/7 Registers610
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Introduction615
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Glitch Filter617
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Prescaler618
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Operating Mode619
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One-Shot Mode619
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Continous Mode620
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Timeout Function621
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Register Update622
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Counter Mode623
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Timer Enable624
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Encoder Mode624
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Debug Mode625
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LPTIM Interrupts626
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LPTIM Registers626
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Introduction636
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Window Option637
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Debug Mode638
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IWDG Registers639
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Introduction645
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Debug Mode648
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WWDG Interrupts648
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WWDG Registers648
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Introduction651
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RTC Register Map693
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Introduction695
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Mode Selection699
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Noise Filters700
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I2C Timings702
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Software Reset705
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Data Transfer706
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Nostretch= 0712
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Nostretch= 1713
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Figure 292. I896
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Figure 298. I900
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Figure 312. I905
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Table 159. I912
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