Figure 137. Dac Sample And Hold Mode Phases Diagram - ST STM32L4x6 Reference Manual

Digital-to-analog converter (DAC)
Refresh phase:
t
refresh
(where N
Hold phase:
D = i
v
i
leak
t
hold
LSI
DAC
Like in normal mode, the sample and hold mode has different configurations.
To enable the output buffer, the MODEx[2:0] bits in DAC_MCR register should be:
–
–
To disabled the output buffer, The MODEx[2:0] bits in DAC_MCR register should be:
–
–
When MODEx[2:0] bits in DAC_MCR register is equal to 111. An internal capacitor "C
will hold the voltage output of the DAC Core and then drive it to on-chip peripherals.
All sample and hold phases are interruptible and any change in DAC_DHRx will trigger
immediately a new sample phase.
550/1693
= 7 μs + (2000 * 100 * 10
= 10 (10 LSB drop during the hold phase)
lsb
* t / C = 0.0073 V (10 LSB of 12bit at 3 V)
leak hold load
= 150 nA (worst case on the IO leakage on all the temperature range)
-9
= 0.0073 * 100 * 10

Figure 137. DAC sample and hold mode phases diagram

Vd
ON
100: DAC is connected to the external pin
101: DAC is connected to external pin and to on chip peripherals
110: DAC is connected to external pin and to on chip peripherals
111: DAC is connected to on chip peripherals
DocID024597 Rev 3
-9
) * ln(2*10) = 606.1 μs
-9
/ (150 * 10 ) = 4.867 ms
ON
RM0351
ON
loadint
"