Flash Power-Down Key Register (Flash_Pdkeyr); Flash Key Register (Flash_Keyr) - ST STM32L4x6 Reference Manual

RM0351
3.7.2

Flash Power-down key register (FLASH_PDKEYR)

Address offset: 0x04
Reset value: 0x0000 0000
Access: no wait state, word access
31 30 29
w w w
15 14 13
w w w
Bits 31:0 PDKEYR: Power-down in Run mode Flash key
3.7.3

Flash key register (FLASH_KEYR)

Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word access
Bit 9 ICEN: Instruction cache enable
0: Instruction cache is disabled
1: Instruction cache is enabled
Bit 8 PRFTEN: Prefetch enable
0: Prefetch disabled
1: Prefetch enabled
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 LATENCY[2:0]: Latency
These bits represent the ratio of the SYSCLK (system clock) period to the Flash
access time.
000: Zero wait state
001: One wait state
010: Two wait sates
011: Three wait sates
100: Four wait sates
others: reserved
28 27 26 25
w w w w
12 11 10 9
w w w w
The following values must be written consecutively to unlock the RUN_PD bit in
FLASH_ACR:
PDKEY1: 0x04152637
PDKEY2: 0xFAFBFCFD
DocID024597 Rev 3
Embedded Flash memory (FLASH)
24 23 22 21
PDKEYR[31:16]
w w w
8 7 6
PDKEYR[15:0]
w w w
20 19 18
w w w w
5 4 3 2
w w w w
17 16
w w
1 0
w w
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