ST STM32F423 Series Manuals

ST STM32F423 Series Manuals

Manuals and User Guides for ST STM32F423 Series. We have 3 ST STM32F423 Series manuals available for free PDF download: Reference Manual, Application Note

ST STM32F423 Series Reference Manual

ST STM32F423 Series Reference Manual (1324 pages)

advanced Arm-based 32-bit MCUs

Brand: ST | Category: Microcontrollers | Size: 15 MB

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ST STM32F423 Series Reference Manual

ST STM32F423 Series Reference Manual (1284 pages)

advanced ARM-based 32-bit MCUs

Brand: ST | Category: Microcontrollers | Size: 14 MB

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50
Documentation Conventions
51
System and Memory Overview
52
I-Bus
53
DMA Peripheral Bus
54
Memory Organization
55
Memory Map and Register Boundary Addresses
56
Embedded SRAM
60
Boot Configuration
61
Table 3. Embedded Bootloader Interfaces
62
Table 4. Memory Mapping Vs. Boot Mode/Physical Remap in STM32F413/423
63
Embedded Flash Memory Interface
64
Embedded Flash Memory
65
Read Interface
66
Adaptive Real-Time Memory Accelerator (ART Accelerator™)
67
Figure 4. Sequential 32-Bit Instruction Execution
68
Erase and Program Operations
69
Program/Erase Parallelism
70
Programming
71
Interrupts
72
Table 10. Description of the Option Bytes
73
Programming User Option Bytes
74
Write Protections
76
Proprietary Code Readout Protection (PCROP)
77
Figure 6. PCROP Levels
78
One-Time Programmable Bytes
79
Flash Interface Registers
80
Flash Key Register (FLASH_KEYR)
81
Flash Status Register (FLASH_SR)
82
Flash Control Register (FLASH_CR)
83
Flash Option Control Register (FLASH_OPTCR)
84
Flash Interface Register Map
87
CRC Introduction
88
CRC Registers
89
Independent Data Register (CRC_IDR)
90
CRC Register Map
91
Power Supplies
92
Independent A/D Converter Supply and Reference Voltage
93
Voltage Regulator
95
Power Supply Supervisor
96
Programmable Voltage Detector (PVD)
97
Low-Power Modes
98
Slowing down System Clocks
100
Sleep Mode
101
Batch Acquisition Mode
102
Stop Mode
103
Table 20. Stop Operating Modes
104
Table 21. Stop Mode Entry and Exit
105
Standby Mode
106
The Stop and Standby Modes
107
Power Control Registers
110
PWR Power Control/Status Register (PWR_CSR)
112
PWR Register Map
114
Reset
115
Power Reset
116
Backup Domain Reset
117
Figure 13. Clock Tree
118
HSE Clock
119
HSI Clock
120
PLL Configuration
121
LSI Clock
122
RTC/AWU Clock
123
Clock-Out Capability
124
Figure 15. Frequency Measurement with TIM5 in Input Capture Mode
125
Figure 16. Frequency Measurement with TIM11 in Input Capture Mode
126
RCC Registers
127
RCC PLL Configuration Register (RCC_PLLCFGR)
129
RCC Clock Configuration Register (RCC_CFGR)
131
RCC Clock Interrupt Register (RCC_CIR)
134
RCC AHB1 Peripheral Reset Register (RCC_AHB1RSTR)
136
For Stm32F413Xx
138
For Stm32F423Xx
139
RCC AHB3 Peripheral Reset Register (RCC_AHB3RSTR)
140
RCC APB2 Peripheral Reset Register (RCC_APB2RSTR)
144
RCC AHB1 Peripheral Clock Enable Register (RCC_AHB1ENR)
146
148
For Stm32F413Xx
148
149
For Stm32F423Xx
149
RCC AHB3 Peripheral Clock Enable Register (RCC_AHB3ENR)
150
RCC_AHB2LPENR) for Stm32F413Xx
159
RCC_AHB2LPENR) for Stm32F423Xx
160
RCC Backup Domain Control Register (RCC_BDCR)
168
RCC Clock Control & Status Register (RCC_CSR)
169
RCC Spread Spectrum Clock Generation Register (RCC_SSCGR)
171
RCC PLLI2S Configuration Register (RCC_PLLI2SCFGR)
172
RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR)
174
RCC Clocks Gated Enable Register (CKGATENR)
176
RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR2)
177
RCC Register Map
178
General-Purpose I/Os (GPIO)
181
Table 25. Port Bit Configuration Table
182
General-Purpose I/O (GPIO)
183
I/O Pin Multiplexer and Mapping
184
Table 26. Flexible SWJ-DP Pin Assignment
185
Figure 18. Selecting an Alternate Function on STM32F413/423
186
I/O Port Control Registers
187
I/O Alternate Function Input/Output
188
Output Configuration
189
Alternate Function Configuration
190
Analog Configuration
191
Selection of RTC Additional Functions
192
GPIO Registers
193
GPIO Port Input Data Register (Gpiox_Idr) (X = A...H)
195
GPIO Alternate Function Low Register (Gpiox_Afrl) (X = A...H)
197
GPIO Register Map
198
I/O Compensation Cell
201
SYSCFG Peripheral Mode Configuration Register (SYSCFG_PMC)
202
SYSCFG External Interrupt Configuration Register
203
204
SYSCFG External Interrupt Configuration Register
204
SYSCFG Configuration Register 2 (SYSCFG_CFGR2)
205
Compensation Cell Control Register (SYSCFG_CMPCR)
206
SYSCFG Configuration Register (SYSCFG_CFGR)
207
SYSCFG Register Map
210
DMA Introduction
211
DMA Functional Description
213
DMA Transactions
214
Table 30. DMA1 Request Mapping
215
Arbiter
216
Figure 25. Peripheral-To-Memory Mode
217
Figure 26. Memory-To-Peripheral Mode
218
Pointer Incrementation
219
Circular Mode
220
Programmable Data Width, Packing/Unpacking, Endianness
221
Table 34. Packing/Unpacking & Endian Behavior (Bit PINC = MINC = 1)
222
Single and Burst Transfers
223
Table 36. FIFO Threshold Configurations
224
DMA Transfer Completion
226
DMA Transfer Suspension
227
Summary of the Possible DMA Configurations
228
Stream Configuration Procedure
229
Error Management
230
DMA Interrupts
231
DMA Registers
232
DMA High Interrupt Status Register (DMA_HISR)
233
DMA Low Interrupt Flag Clear Register (DMA_LIFCR)
234
DMA Stream X Configuration Register (Dma_Sxcr) (X = 0..7)
235
DMA Stream X Number of Data Register (Dma_Sxndtr) (X = 0..7)
238
DMA Stream X Peripheral Address Register (Dma_Sxpar) (X = 0..7)
239
DMA Stream X FIFO Control Register (Dma_Sxfcr) (X = 0..7)
240
DMA Register Map
242
Nested Vectored Interrupt Controller (NVIC)
246
Table 40. Vector Table for STM32F413/423
247
EXTI Main Features
251
Functional Description
253
External Interrupt/Event Line Mapping
254
Interrupt Mask Register (EXTI_IMR)
255
Rising Trigger Selection Register (EXTI_RTSR)
256
Falling Trigger Selection Register (EXTI_FTSR)
257
Software Interrupt Event Register (EXTI_SWIER)
258
Pending Register (EXTI_PR)
259
EXTI Register Map
260
Flexible Static Memory Controller (FSMC)
261
Block Diagram
262
AHB Interface
263
External Device Address Mapping
264
NOR Flash/Psram Controller
265
External Memory Interface Signals
266
Table 45. Non-Multiplexed I/O nor Flash Memory
267
Supported Memories and Transactions
268
Table 49. nor Flash/Psram: Example of Supported Memories and Transactions
269
General Timing Rules
270
Figure 33. Mode1 Read Access Waveforms
271
Table 50. Fsmc_Bcrx Bit Fields
272
Figure 35. Modea Read Access Waveforms
273
Table 52. Fsmc_Bcrx Bit Fields
274
Table 54. Fsmc_Bwtrx Bit Fields
275
Figure 38. Mode2 Write Access Waveforms
276
Table 55. Fsmc_Bcrx Bit Fields
277
Table 57. Fsmc_Bwtrx Bit Fields
278
Table 58. Fsmc_Bcrx Bit Fields
279
Table 59. Fsmc_Btrx Bit Fields
280
Figure 42. Moded Read Access Waveforms
281
Table 61. Fsmc_Bcrx Bit Fields
282
Table 63. Fsmc_Bwtrx Bit Fields
283
Table 64. Fsmc_Bcrx Bit Fields
284
Table 65. Fsmc_Btrx Bit Fields
285
Figure 46. Asynchronous Wait During a Read Access Waveforms
286
Synchronous Transactions
287
Figure 48. Wait Configuration Waveforms
289
Table 66. Fsmc_Bcrx Bit Fields
290
Table 67. Fsmc_Btrx Bit Fields
291
Table 68. Fsmc_Bcrx Bit Fields
292
Table 69. Fsmc_Btrx Bit Fields
293
NOR/PSRAM Controller Registers
294
FSMC Register Map
302
Introduction
304
QUADSPI Pins
305
QUADSPI Command Sequence
306
QUADSPI Signal Interface Protocol Modes
308
Figure 54. an Example of a DDR Command in Quad Mode
309
QUADSPI Indirect Mode
310
QUADSPI Status Flag Polling Mode
311
QUADSPI Memory-Mapped Mode
312
QUADSPI Flash Memory Configuration
313
QUADSPI Usage
314
Sending the Instruction Only Once
316
QUADSPI Busy Bit and Abort Functionality
317
Figure 57. Ncs When CKMODE = 1 in DDR Mode (T = CLK Period)
318
QUADSPI Interrupts
319
QUADSPI Registers
320
QUADSPI Device Configuration Register (QUADSPI_DCR)
323
QUADSPI Status Register (QUADSPI_SR)
324
QUADSPI Flag Clear Register (QUADSPI_FCR)
325
QUADSPI Communication Configuration Register (QUADSPI_CCR)
326
QUADSPI Address Register (QUADSPI_AR)
328
QUADSPI Alternate Bytes Registers (QUADSPI_ABR)
329
QUADSPI Polling Status Mask Register (QUADSPI _PSMKR)
330
QUADSPI Polling Interval Register (QUADSPI _PIR)
331
QUADSPI Register Map
332
ADC Introduction
333
ADC On-Off Control
334
Single Conversion Mode
335
Timing Diagram
336
Scan Mode
337
Discontinuous Mode
338
Data Alignment
339
Channel-Wise Programmable Sampling Time
340
Conversion on External Trigger and Trigger Polarity
341
Data Management
342
Conversions Without DMA and Without Overrun Detection
343
Battery Charge Monitoring
344
ADC Registers
345
ADC Control Register 1 (ADC_CR1)
346
ADC Control Register 2 (ADC_CR2)
348
ADC Sample Time Register 1 (ADC_SMPR1)
349
ADC Sample Time Register 2 (ADC_SMPR2)
350
ADC Watchdog Higher Threshold Register (ADC_HTR)
351
ADC Regular Sequence Register 1 (ADC_SQR1)
352
ADC Regular Sequence Register 3 (ADC_SQR3)
353
ADC Injected Sequence Register (ADC_JSQR)
354
ADC Regular Data Register (ADC_DR)
355
ADC Common Control Register (ADC_CCR)
356
Digital-To-Analog Converter (DAC)
359
Table 79. DAC Pins
360
DAC Functional Description
361
DAC Conversion
362
DAC Output Voltage
363
DMA Request
364
Triangle-Wave Generation
365
Dual DAC Channel Conversion
366
Independent Trigger Without Wave Generation
367
Independent Trigger with Single Triangle Generation
368
Simultaneous Trigger Without Wave Generation
369
Simultaneous Trigger with Single Triangle Generation
370
DAC Registers
371
DAC Software Trigger Register (DAC_SWTRIGR)
374
DAC Channel1 Data Output Register (DAC_DOR1)
378
DAC Status Register (DAC_SR)
379
Digital Filter for Sigma Delta Modulators (DFSDM)
381
DFSDM Main Features
382
DFSDM Implementation
383

ST STM32F423 Series Application Note

ST STM32F423 Series Application Note (50 pages)

Getting started with MCU hardware development

Brand: ST | Category: Motherboard | Size: 1 MB

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