Interconnection Details - ST STM32L4x6 Reference Manual

RM0351
Table 35. STM32L4x6 peripherals interconnect matrix
Source
VREFINT - - -
OPAMP1 - - -
OPAMP2 - - -
DAC1 - - -
DAC2 - - -
HSE - - -
LSE - - 7
MSI - - -
LSI - - -
MCO - - -
EXTI - - -
RTC - - -
COMP1 13 13 13 13
COMP2 13 13 13 13
SYST ERR 14 14 -
USB - - 11
1. Numbers in table are links to corresponding detailed sub-section in
2. The "-" symbol in grayed cells means no interconnect.
9.3

Interconnection details

9.3.1 From timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM8/TIM15/TIM16/TIM17) to
timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM8/TIM15)
Purpose
Some of the TIMx timers are linked together internally for timer synchronization or chaining.
When one timer is configured in Master Mode, it can reset, start, stop or clock the counter of
another timer configured in Slave Mode.
A description of the feature is provided in:
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - 7
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - 13 13 13 8
- - - - 13 13 13 8
- - - - - 14 14 14
- - - - - -
DocID024597 Rev 3
Destination
- - - - 12 -
- - - - 12 12
- - - - 12 12
- - - - - 12 12
- - - - - 12 12
- 7 - - - -
7 - - - - -
- 7 - - - -
7 - - - - -
- 7 - - - -
- - - - 2 2
7 - 8 8 - -
8 - -
8 - -
- - - -
- - - - - -
Section 9.3: Interconnection
Section 27.3.19: Timer
Peripherals interconnect matrix
(1) (2)
(continued)
- - - - - -
- - - - - -
- - - - - -
- 12 12 - -
- - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
2 5 - - 4 4
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
details.
synchronization.
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- - - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - -
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