ST STM32L4x6 Reference Manual page 228

Reset and clock control (RCC)
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
31 30 29 28
LPTIM1 OPAMP DAC1 PWR
EN EN EN EN
rw rw rw rw
15 14 13 12
SPI3 SPI2
Res. Res.
EN EN
rw rw
Bit 31 LPTIM1EN: Low power timer 1 clock enable
Bit 30 OPAMPEN: OPAMP interface clock enable
Bit 29 DAC1EN: DAC1 interface clock enable
Bit 28 PWREN: Power interface clock enable
Bits 27:26 Reserved, must be kept at reset value.
Bit 25 CAN1EN: CAN1 clock enable
Bit 24 Reserved, must be kept at reset value.
Bit 23 I2C3EN: I2C3 clock enable
Bit 22 I2C2EN: I2C2 clock enable
Bit 21 I2C1EN: I2C1 clock enable
228/1693
27 26 25
CAN1
Res. Res.
EN
rw
11 10 9
WWD LCD
Res.
GEN EN
rs rw
Set and cleared by software.
0: LPTIM1 clock disabled
1: LPTIM1 clock enabled
Set and cleared by software.
0: OPAMP interface clock disabled
1: OPAMP interface clock enabled
Set and cleared by software.
0: DAC1 interface clock disabled
1: DAC1 interface clock enabled
Set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enabled
Set and cleared by software.
0: CAN1 clock disabled
1: CAN1 clock enabled
Set and cleared by software.
0: I2C3 clock disabled
1: I2C3 clock enabled
Set and cleared by software.
0: I2C2 clock disabled
1: I2C2 clock enabled
Set and cleared by software.
0: I2C1 clock disabled
1: I2C1 clock enabled
DocID024597 Rev 3
24 23 22 21
I2C3 I2C2 I2C1
Res.
EN EN EN
rw rw rw
8 7 6 5
TIM7
Res. Res. Res.
EN
rw
20 19 18
UART5 UART4 USART3
EN EN EN
rw rw rw
4 3 2
TIM6EN TIM5EN TIM4EN TIM3EN
rw rw rw
RM0351
17 16
USART2
Res.
EN
rw
1 0
TIM2
EN
rw rw