Figure 291. Control Circuit In External Clock Mode 2 + Trigger Mode; Figure 292. Master/Slave Timer Example; Timer Synchronization - ST STM32L4x6 Reference Manual

General-purpose timers (TIM2/TIM3/TIM4/TIM5)
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.
27.3.19

Timer synchronization

The TIMx timers are linked together internally for timer synchronization or chaining. When
one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of
another Timer configured in Slave Mode.
Figure 292: Master/Slave timer example
the master mode selection blocks.
Using one timer as prescaler for another timer
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Figure 291. Control circuit in external clock mode 2 + trigger mode

Figure 292. Master/Slave timer example

DocID024597 Rev 3
presents an overview of the trigger selection and
RM0351