ST STM32L4x6 Manuals

ST STM32L4x6 Manuals

Manuals and User Guides for ST STM32L4x6. We have 1 ST STM32L4x6 manual available for free PDF download: Reference Manual

ST STM32L4x6 Reference Manual

ST STM32L4x6 Reference Manual (1693 pages)

Brand: ST | Category: Microcontrollers | Size: 31 MB

Table of Contents

Table of Contents
2
Documentation Conventions

61
- List of Abbreviations for Registers
  61
- Glossary
  61
- Peripheral Availability
  61
System and Memory Overview

62
- System Architecture
  62
  - S0: I-Bus
    63
  - S1: D-Bus
    63
  - Figure 1. System Architecture
    63
  - S2: S-Bus
    64
  - S3, S4: DMA-Bus
    64
  - Busmatrix
    64
- Memory Organization
  65
- Bit Banding
  71
- Embedded SRAM
  72
- SRAM2 Parity Check
  
  73
  - SRAM2 Write Protection
    73
  - Table 2. SRAM2 Organization
    73
  - Flash Memory Overview
    74
  - SRAM2 Erase
    74
  - SRAM2 Read Protection
    74
  - Boot Configuration
    75
  - Table 3. Boot Modes
    75
  - Table 4. Memory Mapping Versus Boot Mode/Physical Remap
    76
Embedded Flash Memory (FLASH)

78
Firewall (FW)

121
- Firewall Main Features
  121
- Introduction
  121
- Firewall Functional Description
  122
  - Firewall AMBA Bus Snoop
    122
  - Functional Requirements
    122
  - Figure 5. Stm32L4X6 Firewall Connection Schematics
    122
  - Firewall Segments
    123
  - Segment Accesses and Properties
    124
  - Table 15. Segment Accesses According to the Firewall State
    124
  - Firewall Initialization
    125
  - Table 16. Segment Granularity and Area Ranges
    125
  - Firewall States
    126
  - Figure 6. Firewall Functional States
    126
- Firewall Registers
  128
Power Control (PWR)

133
- Power Supplies
  133
  - Independent Analog Peripherals Supply
    134
  - Figure 7. Power Supply Overview
    134
  - Independent I/O Supply Rail
    135
  - Independent USB Transceivers Supply
    135
  - Independent LCD Supply
    136
  - Battery Backup Domain
    136
  - Voltage Regulator
    137
  - Dynamic Voltage Scaling Management
    138
- Power Supply Supervisor
  139
  - Power-On Reset (POR) / Power-Down Reset (PDR) / Brown-Out Reset
    139
    
    (Bor)
    139
  - Programmable Voltage Detector (PVD)
    139
  - Figure 8. Brown-Out Reset Waveform
    139
  - Peripheral Voltage Monitoring (PVM)
    140
  - Table 18. PVM Features
    140
  - Figure 9. PVD Thresholds
    140
- Low-Power Modes
  141
  - Figure 10. Low-Power Modes Possible Transitions
    143
  - Table 19. Low-Power Mode Summary
    144
  - Table 20. Functionalities Depending on the Working Mode
    145
  - Run Mode
    147
  - Low-Power Run Mode (LP Run)
    148
  - Table 21. Low-Power Run
    148
  - Low Power Modes
    149
  - Low-Power Sleep Mode (LP Sleep)
    150
  - Sleep Mode
    150
  - Table 22. Sleep
    150
  - Stop 0 Mode
    151
  - Table 23. Low-Power Sleep
    151
  - Stop 1 Mode
    153
  - Table 24. Stop 0 Mode
    153
  - Stop 2 Mode
    154
  - Table 25. Stop 1 Mode
    154
  - Table 26. Stop 2 Mode
    156
  - Standby Mode
    157
  - Table 27. Standby Mode
    158
  - Shutdown Mode
    159
  - Auto-Wakeup from Low-Power Mode
    160
  - Table 28. Shutdown Mode
    160
- PWR Registers
  161
- Reset
  179
  - Power Reset
    179
  - System Reset
    179
  - Backup Domain Reset
    180
  - Figure 11. Simplified Diagram of the Reset Circuit
    180
Reset and Clock Control (RCC)

179
Cyclic Redundancy Check Calculation Unit (CRC)

337
- CRC Functional Description
  338
- Figure 28. CRC Calculation Unit Block Diagram
  338
- CRC Registers
  339
Flexible Static Memory Controller (FSMC)

343
Voltage Reference Buffer (VREFBUF)

574
- VREFBUF Calibration Control Register (VREFBUF_CCR)
  575
- Table 108. VREFBUF Register Map and Reset Values
  576
Comparator (COMP)

577
Liquid Crystal Display Controller (LCD)

658
- LCD Main Features
  659
- Figure 153. LCD Controller Block Diagram
  660
- LCD Functional Description
  660
  - Frequency Generator
    661
  - Table 128. Example of Frame Rate Calculation
    661
  - Common Driver
    662
  - Figure 154. 1/3 Bias, 1/4 Duty
    662
  - Figure 155. Static Duty Case 1
    663
  - Figure 156. Static Duty Case 2
    664
  - Figure 157. 1/2 Duty, 1/2 Bias
    665
  - Segment Driver
    665
  - Figure 158. 1/3 Duty, 1/3 Bias
    666
  - Figure 159. 1/4 Duty, 1/3 Bias
    667
  - Figure 160. 1/8 Duty, 1/4 Bias
    668
  - Table 129. Blink Frequency
    669
  - Voltage Generator and Contrast Control
    669
  - Figure 161. VLCD Pin for 1/2 1/3 1/4 Bias
    671
  - Figure 162. Deadtime
    672
  - Double Buffer Memory
    673
  - Table 130. Remapping Capability
    674
  - Figure 163. SEG/COM Mux Feature Example
    677
  - Figure 164. Flowchart Example
    678
  - Flowchart
    678
  - Table 131. LCD Behavior in Low-Power Modes
    679
  - Table 132. LCD Interrupt Requests
    679
- LCD Registers
  681
Touch Sensing Controller (TSC)

691
Infrared Interface (IRTIM)

1046
- Figure 348. Independent Watchdog Block Diagram
  1047
  - Introduction
    1047
  - Window Option
    1048
  - Low-Power Freeze
    1049
- IWDG Registers
  1050
  - Prescaler Register (IWDG_PR)
    1051
  - Reload Register (IWDG_RLR)
    1052
  - Status Register (IWDG_SR)
    1053
  - Window Register (IWDG_WINR)
    1054
  - Table 168. IWDG Register Map and Reset Values
    1055
System Window Watchdog (WWDG)

1056
- Figure 349. Watchdog Block Diagram
  1057
  - Enabling the Watchdog
    1057
  - Figure 350. Window Watchdog Timing Diagram
    1058
  - How to Program the Watchdog Timeout
    1058
  - Debug Mode
    1059
- WWDG Registers
  1060
  - Configuration Register (WWDG_CFR)
    1061
  - Table 169. WWDG Register Map and Reset Values
    1062
Real-Time Clock (RTC)

1063
- RTC Main Features
  1064
- RTC Functional Description
  1065
  - Gpios Controlled by the RTC
    1066
  - Table 170. RTC Pin PC13 Configuration
    1066
  - Clock and Prescalers
    1067
  - Table 171. RTC_OUT Mapping
    1067
  - Real-Time Clock and Calendar
    1068
  - Programmable Alarms
    1069
  - RTC Initialization and Configuration
    1070
  - Reading the Calendar
    1071
  - Resetting the RTC
    1072
  - RTC Synchronization
    1073
  - RTC Smooth Digital Calibration
    1074
  - Time-Stamp Function
    1076
  - Tamper Detection
    1077
  - Calibration Clock Output
    1079
  - Table 172. Effect of Low-Power Modes on RTC
    1079
- RTC Interrupts
  1080
- RTC Registers
  1081
- Table 173. Interrupt Control Bits
  1081
- I2C Registers
  1160
  - Control Register 2 (I2C_CR2)
    1164
  - Own Address 1 Register (I2C_OAR1)
    1167
  - Own Address 2 Register (I2C_OAR2)
    1168
  - Timing Register (I2C_TIMINGR)
    1169
  - Timeout Register (I2C_TIMEOUTR)
    1170
  - Interrupt and Status Register (I2C_ISR)
    1171
  - Interrupt Clear Register (I2C_ICR)
    1173
  - PEC Register (I2C_PECR)
    1174
  - Receive Data Register (I2C_RXDR)
    1175
  - Table 190. I2C Register Map and Reset Values
    1176
Transmitter (USART)

1178
- USART Extended Features
  1179
- Table 191. Stm32L4X6 USART/UART/LPUART Features
  1180
- USART Implementation
  1180
- USART Registers
  1222
  - Control Register 2 (Usartx_Cr2)
    1225
  - Control Register 3 (Usartx_Cr3)
    1229
  - Baud Rate Register (Usartx_Brr)
    1233
  - Receiver Timeout Register (Usartx_Rtor)
    1234
  - Request Register (Usartx_Rqr)
    1235
  - Interrupt and Status Register (Usartx_Isr)
    1236
  - Interrupt Flag Clear Register (Usartx_Icr)
    1241
  - Receive Data Register (Usartx_Rdr)
    1242
  - Table 199. USART Register Map and Reset Values
    1243
Transmitter (LPUART)

1245
- LPUART Main Features
  1246
- LPUART Functional Description
  1247
  - Figure 408. LPUART Block Diagram
    1248
  - LPUART Character Description
    1248
  - Figure 409. Word Length Programming
    1250
  - Figure 410. Configurable Stop Bits
    1251
  - LPUART Transmitter
    1251
  - Figure 411. TC/TXE Behavior When Transmitting
    1253
  - LPUART Receiver
    1253
  - LPUART Baud Rate Generation
    1256
  - Multiprocessor Communication Using LPUART
    1257
  - Table 200. Error Calculation for Programmed Baudrates at Fck = 32,768 Khz
    1257
  - Figure 412. Mute Mode Using Idle Line Detection
    1258
  - Figure 413. Mute Mode Using Address Mark Detection
    1259
  - LPUART Parity Control
    1259
  - Table 201. Frame Formats
    1259
  - Single-Wire Half-Duplex Communication Using LPUART
    1260
    
    Figure 414. Transmission Using DMA
    1261
    
    Figure 415. Reception Using DMA
    1262
    
    Figure 416. Hardware Flow Control between 2 Lpuarts
    1263
    
    Figure 417. RS232 RTS Flow Control
    1263
    
    Using LPUART
    1263
    
    Figure 418. RS232 CTS Flow Control
    1264
    
    Table 202. Effect of Low-Power Modes on the LPUART
    1265
  - Wakeup from Stop Mode Using LPUART
    1265
  - Table 203. LPUART Interrupt Requests
    1266
- LPUART Interrupts
  1266
- Figure 419. LPUART Interrupt Mapping Diagram
  1267
- LPUART Registers
  1268
  - Control Register 2 (LPUART_CR2)
    1271
  - Control Register 3 (LPUART_CR3)
    1273
  - Baud Rate Register (LPUART_BRR)
    1275
  - Interrupt & Status Register (LPUART_ISR)
    1276
  - Interrupt Flag Clear Register (LPUART_ICR)
    1279
  - Receive Data Register (LPUART_RDR)
    1280
  - Table 204. LPUART Register Map and Reset Values
    1282
  - Introduction
    1283
  - Table 205. Stm32L4X6 SPI Implementation
    1284
  - Figure 420. SPI Block Diagram
    1284
- SPI Functional Description
  1284
- SPI Interrupts
  1308
- SPI Registers
  1309
  - SPI Control Register 2 (Spix_Cr2)
    1311
  - SPI Status Register (Spix_Sr)
    1314
  - SPI Data Register (Spix_Dr)
    1315
  - SPI Rx CRC Register (Spix_Rxcrcr)
    1316
  - Table 207. SPI Register Map and Reset Values
    1317
  - Introduction
    1318
- SAI Main Features
  1319
- Figure 436. Functional Block Diagram
  1320
- SAI Functional Description
  1320
  - Main SAI Modes
    1321
  - SAI Synchronization Mode
    1322
  - Table 208. External Synchronization Selection
    1323
  - Figure 437. Audio Frame
    1323
  - Audio Data Size
    1323
  - Figure 438. FS Role Is Start of Frame + Channel Side Identification (FSDEF = TRIS = 1)
    1325
  - Figure 439. FS Role Is Start of Frame (FSDEF = 0)
    1326
  - Slot Configuration
    1326
  - Figure 440. Slot Size Configuration with FBOFF = 0 in Sai_Xslotr
    1327
  - Figure 441. First Bit Offset
    1327
  - Figure 442. Audio Block Clock Generator Overview
    1328
  - SAI Clock Generator
    1328
  - Table 209. Example of Possible Audio Frequency Sampling Range
    1329
  - Internal Fifos
    1330
  - Figure 443. AC'97 Audio Frame
    1332
  - AC'97 Link Controller
    1332
  - Figure 444. Example of Typical AC'97 Configuration on Devices Featuring at Least
    1333
  - Embedded Sais (Three External AC'97 Decoders)
    1333
  - Figure 445. SPDIF Format
    1334
  - SPDIF Output
    1334
  - Table 210. SOPD Pattern
    1335
  - Table 211. Parity Bit Calculation
    1335
  - Figure 446. Sai_Xdr Register Ordering
    1335
  - Table 212. Audio Sampling Frequency Versus Symbol Rates (SHARK)
    1336
  - Specific Features
    1336
  - Figure 447. Data Companding Hardware in an Audio Block in the SAI
    1338
  - Figure 448. Tristate Strategy on SD Output Line on an Inactive Slot
    1340
  - Figure 449. Tristate on Output Data Line in a Protocol Like I2S
    1341
  - Error Flags
    1341
  - Figure 450. Overrun Detection Error
    1342
  - Figure 451. FIFO Underrun Event
    1342
  - Disabling the SAI
    1344
  - Table 213. SAI Interrupt Sources
    1345
- SAI Interrupts
  1345
- SAI Registers
  1346
  - Configuration Register 2 (SAI_ACR2 / SAI_BCR2)
    1350
  - Frame Configuration Register (SAI_AFRCR / SAI_BFRCR)
    1352
  - Slot Register (SAI_ASLOTR / SAI_BSLOTR)
    1354
  - Interrupt Mask Register 2 (SAI_AIM / SAI_BIM)
    1356
  - Status Register (SAI_ASR / SAI_BSR)
    1358
  - Clear Flag Register (SAI_ACLRFR / SAI_BCLRFR)
    1360
  - Table 214. SAI Register Map and Reset Values
    1361
  - Data Register (SAI_ADR / SAI_BDR)
    1361
  - Figure 452. S1 Signal Coding
    1363
  - Figure 453. S2 Signal Coding
    1363
  - Introduction
    1363
- SWPMI Main Features
  1364
- Figure 454. SWPMI Block Diagram
  1365
- SWPMI Functional Description
  1365
- SWPMI Registers
  1381
- SDMMC Main Features
  1393
- Figure 464. "No Response" and "No Data" Operations
  1394
- Figure 465. (Multiple) Block Read Operation
  1394
- Figure 466. (Multiple) Block Write Operation
  1394
- Figure 467. Sequential Read Operation
  1395
- Figure 468. Sequential Write Operation
  1395
- Figure 469. SDMMC Block Diagram
  1395
- SDMMC Functional Description
  1395
  - Table 219. SDMMC I/O Definitions
    1396
  - Figure 470. SDMMC Adapter
    1397
  - Figure 471. Control Unit
    1398
  - Figure 472. SDMMC_CK Clock Dephasing (BYPASS = 0)
    1399
  - Figure 473. SDMMC Adapter Command Path
    1399
  - Figure 474. Command Path State Machine (SDMMC)
    1400
  - Figure 475. SDMMC Command Transfer
    1401
  - Table 220. Command Format
    1401
  - Table 221. Short Response Format
    1402
  - Table 222. Long Response Format
    1402
  - Table 223. Command Path Status Flags
    1402
  - Figure 476. Data Path
    1403
  - Figure 477. Data Path State Machine (DPSM)
    1404
  - Table 224. Data Token Format
    1405
  - Table 225. DPSM Flags
    1406
  - Table 226. Transmit FIFO Status Flags
    1407
  - Table 227. Receive FIFO Status Flags
    1407
  - SDMMC APB2 Interface
    1408
- Card Functional Description
  1409
  - Operating Voltage Range Validation
    1410
  - Block Write
    1411
  - Block Read
    1412
  - Erase: Group Erase and Sector Erase
    1414
  - Table 228. Card Status
    1418
  - Card Status Register
    1418
  - SD Status Register
    1420
  - Table 229. SD Status
    1421
  - Table 230. Speed Class Code Field
    1422
  - Table 231. Performance Move Field
    1422
  - Table 232. AU_SIZE Field
    1423
  - Table 233. Maximum au Size
    1423
  - Table 234. Erase Size Field
    1424
  - Table 235. Erase Timeout Field
    1424
  - Table 236. Erase Offset Field
    1424
  - SD I/O Mode
    1425
  - Commands and Responses
    1426
  - Table 237. Block-Oriented Write Commands
    1427
  - Table 238. Block-Oriented Write Protection Commands
    1427
  - Table 239. Erase Commands
    1428
  - Table 240. I/O Mode Commands
    1428
  - Table 241. Lock Card
    1428
  - Table 242. Application-Specific Commands
    1429
  - Table 243. R1 Response
    1429
- Response Formats
  1429
  - R2 (CID, CSD Register)
    1430
  - Table 244. R2 Response
    1430
  - R3 (OCR Register)
    1431
  - Table 245. R3 Response
    1431
  - Table 246. R4 Response
    1431
  - Table 247. R4B Response
    1431
  - R5 (Interrupt Request)
    1432
  - Table 248. R5 Response
    1432
  - Table 249. R6 Response
    1433
- SDIO I/O Card-Specific Operations
  1433
  - SDIO Read Wait Operation by Stopping SDMMC_CK
    1434
- SDMMC Registers
  1435
  - SDMMC Argument Register (SDMMC_ARG)
    1437
  - SDMMC Command Response Register (SDMMC_RESPCMD)
    1438
  - Table 250. Response Type and Sdmmc_Respx Registers
    1439
  - SDMMC Data Timer Register (SDMMC_DTIMER)
    1439
  - SDMMC Data Length Register (SDMMC_DLEN)
    1440
  - SDMMC Data Counter Register (SDMMC_DCOUNT)
    1442
  - SDMMC Interrupt Clear Register (SDMMC_ICR)
    1443
  - SDMMC Mask Register (SDMMC_MASK)
    1445
  - SDMMC FIFO Counter Register (SDMMC_FIFOCNT)
    1447
  - SDMMC Data FIFO Register (SDMMC_FIFO)
    1448
  - Table 251. SDMMC Register Map
    1449
  - Introduction
    1451
  - Figure 478. CAN Network Topology
    1452
- Bxcan General Description
  1452
  - Acceptance Filters
    1453
  - Sleep Mode (Low-Power)
    1454
  - Figure 479. Bxcan Operating Modes
    1455
- Test Mode
  1455
- Figure 480. Bxcan in Silent Mode
  1456
- Figure 481. Bxcan in Loop Back Mode
  1456
- Behavior in Debug Mode
  1457
  - Figure 482. Bxcan in Combined Mode
    1457
  - Figure 483. Transmit Mailbox States
    1458
  - Figure 484. Receive FIFO States
    1459
  - Time Triggered Communication Mode
    1459
  - Identifier Filtering
    1460
  - Figure 485. Filter Bank Scale Configuration - Register Organization
    1462
  - Figure 486. Example of Filter Numbering
    1463
  - Figure 487. Filtering Mechanism - Example
    1464
  - Message Storage
    1464
  - Figure 488. CAN Error State Diagram
    1465
  - Table 252. Transmit Mailbox Mapping
    1465
  - Table 253. Receive Mailbox Mapping
    1465
  - Error Management
    1466
  - Figure 489. Bit Timing
    1467
  - Figure 490. CAN Frames
    1468
  - Figure 491. Event Flags and Interrupt Generation
    1469
- Bxcan Interrupts
  1469
- CAN Registers
  1470
  - CAN Mailbox Registers
    1480
  - Figure 492. Can Mailbox Registers
    1481
  - CAN Filter Registers
    1487
  - Table 254. Bxcan Register Map and Reset Values
    1491
  - Introduction
    1495
  - Host-Mode Features
    1496
  - Table 255. USB_OTG Implementation for Stm32L4Xx
    1497
  - Peripheral-Mode Features
    1497
  - Figure 493. OTG Full-Speed Block Diagram
    1498
- USB OTG Functional Description
  1498
  - Full-Speed OTG PHY
    1499
  - Figure 494. OTG_FS A-B Device Connection
    1500
- OTG Dual Role Device (DRD)
  1500
  - SRP Dual Role Device
    1501
  - Figure 495. USB_FS Peripheral-Only Connection
    1502
  - SRP-Capable Peripheral
    1502
  - Peripheral Endpoints
    1503
- USB Host
  1505
  - Figure 496. USB_FS Host-Only Connection
    1506
  - SRP-Capable Host
    1506
  - Host Channels
    1508
  - Host Scheduler
    1509
  - Figure 497. SOF Connectivity (SOF Trigger Output to TIM and ITR1 Connection)
    1510
- Power Options
  1511
- Dynamic Update of the OTG_HFIR Register
  1512
- OTG_FS System Performance
  1516
- Figure 501. Interrupt Hierarchy
  1517
- OTG_FS Interrupts
  1517
- Table 256. Core Global Control and Status Registers (Csrs)
  1518
- Table 257. Host-Mode Control and Status Registers (Csrs)
  1519
- Table 258. Device-Mode Control and Status Registers
  1520
- OTG_FS Registers
  1522
  - OTG Interrupt Register (OTG_GOTGINT)
    1524
  - OTG AHB Configuration Register (OTG_GAHBCFG)
    1526
  - Table 261. TRDT Values
    1528
  - OTG Reset Register (OTG_GRSTCTL)
    1528
  - OTG Core Interrupt Register (OTG_GINTSTS)
    1530
  - OTG Interrupt Mask Register (OTG_GINTMSK)
    1534
  - OTG_FS Receive Status Debug Read/Otg Status Read and Pop Registers (OTG_GRXSTSR/OTG_GRXSTSP)
    1537
  - OTG Receive FIFO Size Register (OTG_GRXFSIZ)
    1539
  - OTG General Core Configuration Register (OTG_GCCFG)
    1542
  - OTG Core ID Register (OTG_CID)
    1543
  - OTG Core LPM Configuration Register (OTG_GLPMCFG)
    1544
  - OTG Power down Register (OTG_GPWRDN)
    1548
  - Host-Mode Registers
    1551
  - OTG Host Frame Interval Register (OTG_HFIR)
    1552
  - OTG Host All Channels Interrupt Register (OTG_HAINT)
    1555
  - OTG Host Port Control and Status Register (OTG_HPRT)
    1556
  - Device-Mode Registers
    1563
  - OTG Device Control Register (OTG_DCTL)
    1564
  - Table 262. Minimum Duration for Soft Disconnect
    1565
  - OTG Device Status Register (OTG_DSTS)
    1566
  - OTG Device All Endpoints Interrupt Register (OTG_DAINT)
    1568
  - OTG Power and Clock Gating Control Register (OTG_PCGCCTL)
    1585
  - Table 263. OTG_FS Register Map and Reset Values
    1586
  - Core Initialization
    1594
  - Host Initialization
    1595
  - Host Programming Model
    1596
  - Figure 502. Transmit FIFO Write Task
    1597
  - Figure 503. Receive FIFO Read Task
    1598
  - Figure 504. Normal Bulk/Control OUT/SETUP
    1599
  - Figure 505. Bulk/Control in Transactions
    1603
  - Figure 506. Normal Interrupt out
    1606
  - Figure 507. Normal Interrupt in
    1610
  - Figure 508. Isochronous out Transactions
    1612
  - Figure 509. Isochronous in Transactions
    1615
  - Device Programming Model
    1616
  - Figure 510. Receive FIFO Packet Read
    1620
  - Figure 511. Processing a SETUP Packet
    1622
  - Figure 512. Bulk out Transaction
    1628
  - Worst Case Response Time
    1636
  - Figure 513. TRDT Max Timing Case
    1638
  - OTG Programming Model
    1638
  - Figure 514. A-Device SRP
    1639
  - Figure 515. B-Device SRP
    1640
  - Figure 516. A-Device HNP
    1641
  - Figure 517. B-Device HNP
    1643
  - Figure 518. Block Diagram of STM32 MCU and Cortex ® -M4-Level Debug Support
    1645
  - Reference ARM® Documentation
    1646
  - Figure 519. SWJ Debug Port
    1647
  - Mechanism to Select the JTAG-DP or the SW-DP
    1647
  - Table 264. SWJ Debug Port Pins
    1648
  - Table 265. Flexible SWJ-DP Pin Assignment
    1648
  - Internal Pull-Up and Pull-Down on JTAG Pins
    1649
  - Using Serial Wire and Releasing the Unused Debug Pins as Gpios
    1650
  - Figure 520. JTAG TAP Connections
    1651
- Table 259. Data FIFO (DFIFO) Access Register Map
  1522
- Table 260. Power and Clock Gating Control and Status Registers
  1522
- ID Codes and Locking Mechanism
  1651
- SW Debug Port
  1655
  - SW-DP State Machine (Reset, Idle States, ID Code)
    1656
  - Table 269. ACK Response (3 Bits)
    1656
  - Table 270. DATA Transfer (33 Bits)
    1656
  - Table 271. SW-DP Registers
    1657
  - SW-AP Registers
    1658
  - Table 272. Cortex ® -M4 AHB-AP Registers
    1658
  - Table 273. Core Debug Registers
    1659
- FPB (Flash Patch Breakpoint)
  1660
- ITM (Instrumentation Trace Macrocell)
  1661
- Table 274. Main ITM Registers
  1661
- ETM (Embedded Trace Macrocell)
  1663
- Table 275. Main ETM Registers
  1663
- TPIU (Trace Port Interface Unit)
  1671
  - Table 277. Synchronous TRACE Pin Assignment
    1672
  - Table 278. Flexible TRACE Pin Assignment
    1672
  - TPUI Formatter
    1673
  - TPUI Frame Synchronization Packets
    1674
  - Asynchronous Mode
    1675
  - Table 279. Important TPIU Registers
    1676
  - Example of Configuration
    1677
  - Table 280. DBG Register Map and Reset Values
    1678
Device Electronic Signature

1679
- Flash Size Data Register
  1680
- Package Data Register
  1681
- Table 281. Document Revision History
  1688

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