Tim1/Tim8 Capture/Compare Mode Register 1 (Timx_Ccmr1) - ST STM32L4x6 Reference Manual

RM0351
Bit 2 CC2G: Capture/Compare 2 generation
Refer to CC1G description
Bit 1 CC1G: Capture/Compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the
CC1IF flag was already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Reinitialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if
the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload
value (TIMx_ARR) if DIR=1 (downcounting).
26.4.7

TIM1/TIM8 capture/compare mode register 1 (TIMx_CCMR1)

Address offset: 0x18
Reset value: 0x0000 0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its
function when the channel is configured in input. So you must take care that the same bit
can have a different meaning for the input stage and for the output stage.
31 30 29
Res. Res. Res. Res.
15 14 13
OC2
OC2M[2:0]
CE
IC2F[3:0]
rw rw rw
Output compare mode:
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 OC2M[3]: Output Compare 2 mode - bit 3
Bits 23:17 Reserved, must be kept at reset value.
Bits16 OC1M[3]: Output Compare 1 mode - bit 3
Refer to OC1M description on bits 6:4
28 27 26 25
Res. Res. Res.
12 11 10 9
OC2 OC2
PE FE
CC2S[1:0]
IC2PSC[1:0]
rw rw rw rw
24 23 22
OC2M[3] Res. Res.
Res.
8 7 6
OC1
CE
IC1F[3:0]
rw rw rw
DocID024597 Rev 3
Advanced-control timers (TIM1/TIM8)
21 20 19
Res. Res. Res. Res.
5 4 3
OC1 OC1
OC1M[2:0]
PE
IC1PSC[1:0]
rw rw rw
18 17 16
Res. OC1M[3]
Res.
2 1 0
FE
CC1S[1:0]
rw rw rw
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