Table 97. Adc Interrupts Per Each Adc - ST STM32L4x6 Reference Manual

Analog-to-digital converters (ADC)
actual VDDA voltage using the internal reference
Where:
• VREFINT_CAL is the VREFINT calibration value
•
ADCx_DATA is the value measured by the ADC on channel x (right-aligned)
• VREFINT_DATA is the actual VREFINT output value converted by the ADC
•
FULL_SCALE is the maximum digital value of the ADC output. For example with 12-bit
resolution, it will be 2
Note: If ADC measurements are done using an output format other than 12 bit right-aligned, all the
parameters must first be converted to a compatible format before the calculation is done.
16.4 ADC interrupts
For each ADC, an interrupt can be generated:
•
After ADC power-up, when the ADC is ready (flag ADRDY)
•
On the end of any conversion for regular groups (flag EOC)
•
On the end of a sequence of conversion for regular groups (flag EOS)
•
On the end of any conversion for injected groups (flag JEOC)
•
On the end of a sequence of conversion for injected groups (flag JEOS)
•
When an analog watchdog detection occurs (flag AWD1, AWD2 and AWD3)
•
When the end of sampling phase occurs (flag EOSMP)
•
When the data overrun occurs (flag OVR)
•
When the injected sequence context queue overflows (flag JQOVF)
Separate interrupt enable bits are available for flexibility.
ADC ready
End of conversion of a regular group
End of sequence of conversions of a regular group
End of conversion of a injected group
End of sequence of conversions of an injected group
Analog watchdog 1 status bit is set
Analog watchdog 2 status bit is set
Analog watchdog 3 status bit is set
End of sampling phase
Overrun
Injected context queue overflows
502/1693
×
3.0 V VREFINT_CAL
------------------------------------------------------------------------------------------------------- -
V
=
CHANNELx
VREFINT_DATA
12
- 1 = 4095 or with 8-bit resolution, 2

Table 97. ADC interrupts per each ADC

Interrupt event
DocID024597 Rev 3
voltage, resulting in the following formula:
×
ADCx_DATA
×
FULL_SCALE
8
- 1 = 255.
Event flag
ADRDY
EOC
EOS
JEOC
JEOS
AWD1
AWD2
AWD3
EOSMP
OVR
JQOVF
RM0351
Enable control bit
ADRDYIE
EOCIE
EOSIE
JEOCIE
JEOSIE
AWD1IE
AWD2IE
AWD3IE
EOSMPIE
OVRIE
JQOVFIE