Tsc Registers - ST STM32L4x6 Reference Manual

Touch sensing controller (TSC)
23.6

TSC registers

Refer to
register descriptions.
The peripheral registers can be accessed by words (32-bit).
23.6.1 TSC control register (TSC_CR)
Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
CTPH[3:0]
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15 14 13
SSPSC PGPSC[2:0]
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Bits 31:28 CTPH[3:0]: Charge transfer pulse high
These bits are set and cleared by software. They define the duration of the high state of the
charge transfer pulse (charge of C
Note: These bits must not be modified when an acquisition is ongoing.
Bits 27:24 CTPL[3:0]: Charge transfer pulse low
These bits are set and cleared by software. They define the duration of the low state of the
charge transfer pulse (transfer of charge from C
Note: These bits must not be modified when an acquisition is ongoing.
Note: Some configurations are forbidden. Please refer to the
Bits 23:17 SSD[6:0]: Spread spectrum deviation
These bits are set and cleared by software. They define the spread spectrum deviation which
consists in adding a variable number of periods of the SSCLK clock to the charge transfer
pulse high state.
Note: These bits must not be modified when an acquisition is ongoing.
700/1693
Section 1.1 on page 61
28 27 26 25
CTPL[3:0]
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12 11 10 9
Res. Res. Res.
rw
0000: 1x t
PGCLK
0001: 2x t
PGCLK
...
1111: 16x t
PGCLK
0000: 1x t
PGCLK
0001: 2x t
PGCLK
...
1111: 16x t
PGCLK
acquisition sequence
0000000: 1x t
SSCLK
0000001: 2x t
SSCLK
...
1111111: 128x t
SSCLK
of the reference manual for a list of abbreviations used in
24 23 22
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8 7 6
Res. MCV[2:0]
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).
X
to C
X
for details.
DocID024597 Rev 3
21 20 19 18
SSD[6:0]
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5 4 3 2
SYNC
IODEF AM
POL
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).
S
Section 23.3.4: Charge transfer
RM0351
17 16
SSE
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1 0
START TSCE
rw rw