Lcd Clear Register (Lcd_Clr) - ST STM32L4x6 Reference Manual

Liquid crystal display controller (LCD)
22.6.4

LCD clear register (LCD_CLR)

Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:4 Reserved, must be kept at reset value
Bit 3 UDDC: Update display done clear
This bit is written by software to clear the UDD flag in the LCD_SR register.
Bit 2 Reserved, must be kept at reset value
Bit 1 SOFC: Start of frame flag clear
This bit is written by software to clear the SOF flag in the LCD_SR register.
Bit 0 Reserved, must be kept at reset value
22.6.5 LCD display memory (LCD_RAM)
Address offset: 0x14 to 0x50
Reset value: 0x0000 0000
31 30 29 28
rw rw rw rw
15 14 13 12
rw rw rw rw
Bits 31:0 SEGMENT_DATA[31:0]
Each bit corresponds to one pixel of the LCD display.
688/1693
27 26 25
Res. Res. Res.
11 10 9
Res. Res. Res.
0: No effect
1: Clear UDD flag
0: No effect
1: Clear SOF flag
27 26 25
rw rw rw
11 10 9
rw rw rw
0: Pixel inactive
1: Pixel active
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
24 23 22
SEGMENT_DATA[31:16]
rw rw rw
8 7 6
SEGMENT_DATA[15:0]
rw rw rw
DocID024597 Rev 3
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res.
UDDC
w
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
RM0351
17 16
Res. Res.
1 0
Res.
SOFC
w
17 16
rw rw
1 0
rw rw