ST STM32L4x6 Reference Manual page 101

RM0351
Level 1: Read protection
This is the default protection level when RDP option byte is erased. It is defined as well
when RDP value is at any value different from 0xAA and 0xCC, or even if the complement is
not correct.
•
User mode: Code executing in user mode (Boot Flash) can access Flash main
memory, option bytes, SRAM2 and backup registers with all operations.
•
Debug, boot RAM and boot loader modes: In debug mode or when code is running
from boot RAM or boot loader, the Flash main memory, the backup registers
(RTC_BKPxR in the RTC) and the SRAM2 are totally inaccessible. In these modes, a
read or write access to the Flash generates a bus error and a Hard Fault interrupt.
Level 2: No debug
In this level, the protection level 1 is guaranteed. In addition, the Cortex
boot from RAM (boot RAM mode) and the boot from System memory (boot loader mode)
are no more available. In user execution mode (boot FLASH mode), all operations are
allowed on the Flash Main memory. On the contrary, only read operations can be performed
on the option bytes.
Option bytes cannot be programmed nor erased. Thus, the level 2 cannot be removed at all:
it is an irreversible operation. When attempting to modify the options bytes, the protection
error flag WRPERR is set in the Flash_SR register and an interrupt can be generated.
Note: The debug feature is also disabled under reset.
STMicroelectronics is not able to perform analysis on defective parts on which the level 2
protection has been set.
Changing the Read protection level
It is easy to move from level 0 to level 1 by changing the value of the RDP byte to any value
(except 0xCC). By programming the 0xCC value in the RDP byte, it is possible to go to level
2 either directly from level 0 or from level 1. Once in level 2, it is no more possible to modify
the Read protection level.
When the RDP is reprogrammed to the value 0xAA to move from Level 1 to Level 0, a mass
erase of the Flash main memory is performed if PCROP_RDP is set in the
PCROP End address register
the RTC) and the SRAM2 are also erased. The user options except PCROP protection are
set to their previous values copied from FLASH_OPTR, FLASH_WRPxyR (x=1, 2 and y =A
or B). PCROP is disable. The OTP area is not affected by mass erase and remains
unchanged.
If the bit PCROP_RDP is cleared in the FLASH_PCROP1ER, the full mass erase is
replaced by a partial mass erase that is successive page erases in the bank where PCROP
is active, except for the pages protected by PCROP. This is done in order to keep the
PCROP code. If PCROP is active for both banks, both banks are erased by page erases.
Only when both banks are erased, options are re-programmed with their previous values.
This is also true for FLASH_PCROPxSR and FLASH_PCROPxER registers (x=1,2).
Note: Full Mass Erase or Partial Mass Erase is performed only when Level 1 is active and Level 0
requested. When the protection level is increased (0->1, 1->2, 0->2) there is no mass erase.
To validate the protection level change, the option bytes must be reloaded through the
OBL_LAUNCH bit in Flash control register.
(FLASH_PCROP1ER). The backup registers (RTC_BKPxR in
DocID024597 Rev 3
Embedded Flash memory (FLASH)
®
-M4 debug port, the
Flash Bank 1
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