ST STM32L4x6 Reference Manual page 1018

Basic timers (TIM6/TIM7)
Bit 7 ARPE: Auto-reload preload enable
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 OPM: One-pulse mode
Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
Bit 0 CEN: Counter enable
Note: Gated mode can work only if the CEN bit has been previously set by software.
CEN is cleared automatically in one-pulse mode, when an update event occurs.
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0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the CEN bit).
0: Any of the following events generates an update interrupt or DMA request if enabled.
These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if
a hardware reset is received from the slave mode controller.
0: Counter disabled
1: Counter enabled
However trigger mode can set the CEN bit automatically by hardware.
DocID024597 Rev 3
RM0351