Syscfg Configuration Register 2 (Syscfg_Cfgr2) - ST STM32L4x6 Reference Manual

RM0351
8.2.8

SYSCFG configuration register 2 (SYSCFG_CFGR2)

Address offset: 0x1C
System reset value: 0x0000 0000
31 30 29
Res Res Res
15 14 13
Res Res Res
Bits 31:9 Reserved, must be kept at reset value
8.2.9 SYSCFG SRAM2 write protection register (SYSCFG_SWPR)
Address offset: 0x20
28 27 26 25
Res Res Res Res
12 11 10 9
Res Res Res Res
Bit 8 SPF: SRAM2 parity error flag
This bit is set by hardware when an SRAM2 parity error is detected. It is cleared
by software by writing '1'.
0: No SRAM2 parity error detected
1: SRAM2 parity error detected
Bits 7:4 Reserved, must be kept at reset value
Bit 3 ECCL: ECC Lock
This bit is set by software and cleared only by a system reset. It can be used to
enable and lock the Flash ECC error connection to TIM1/8/15/16/17 Break input.
0: ECC error disconnected from TIM1/8/15/16/17 Break input.
1: ECC error connected to TIM1/8/15/16/17 Break input.
Bit 2 PVDL: PVD lock enable bit
This bit is set by software and cleared only by a system reset. It can be used to
enable and lock the PVD connection to TIM1/8/15/16/17 Break input, as well as
the PVDE and PLS[2:0] in the PWR_CR2 register.
0: PVD interrupt disconnected from TIM1/8/15/16/17 Break input. PVDE and
PLS[2:0] bits can be programmed by the application.
1: PVD interrupt connected to TIM1/8/15/16/17 Break input, PVDE and PLS[2:0]
bits are read only.
Bit 1 SPL: SRAM2 parity lock bit
This bit is set by software and cleared only by a system reset. It can be used to
enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17
Break inputs.
0: SRAM2 parity error signal disconnected from TIM1/8/15/16/17 Break inputs
1: SRAM2 parity error signal connected to TIM1/8/15/16/17 Break inputs
®
Bit 0 CLL: Cortex -M4 LOCKUP (Hardfault) output enable bit
This bit is set by software and cleared only by a system reset. It can be used to
enable and lock the connection of Cortex
TIM1/8/15/16/17 Break input
®
0: Cortex -M4 LOCKUP output disconnected from TIM1/8/15/16/17 Break inputs
®
1: Cortex -M4 LOCKUP output connected to TIM1/8/15/16/17 Break inputs
System configuration controller (SYSCFG)
24 23 22
Res Res Res
8 7 6
SPF Res Res
rc_w1
DocID024597 Rev 3
21 20 19 18
Res Res Res Res
5 4 3 2
Res Res ECCL PVDL
rs rs
®
-M4 LOCKUP (Hardfault) output to
17 16
Res Res
1 0
SPL CLL
rs rs
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