Timx Capture/Compare Mode Register 1 (Timx_Ccmr1) - ST STM32L4x6 Reference Manual

RM0351
27.4.7

TIMx capture/compare mode register 1 (TIMx_CCMR1)

Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its
function when the channel is configured in input. So you must take care that the same bit
can have a different meaning for the input stage and for the output stage.
31 30 29
Res. Res. Res. Res.
15 14 13
OC2CE OC2M[2:0]
IC2F[3:0]
rw rw rw
Output compare mode
Bits 31:25 Reserved, always read as 0.
Bit 24 OC2M[3]: Output Compare 2 mode - bit 3
Bits 23:17 Reserved, always read as 0.
Bit 16 OC1M[3]: Output Compare 1 mode - bit 3
Bit 15 OC2CE: Output compare 2 clear enable
Bits 14:12 OC2M[2:0]: Output compare 2 mode
refer to OC1M description on bits 6:4
Bit 11 OC2PE: Output compare 2 preload enable
Bit 10 OC2FE: Output compare 2 fast enable
Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
Bit 7 OC1CE: Output compare 1 clear enable
OC1CE: Output Compare 1 Clear Enable
28 27 26 25
Res. Res. Res.
12 11 10 9
OC2PE OC2FE
CC2S[1:0]
IC2PSC[1:0]
rw rw rw rw
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through the TS bit (TIMx_SMCR register)
0: OC1Ref is not affected by the ETRF input
1: OC1Ref is cleared as soon as a High level is detected on ETRF input
General-purpose timers (TIM2/TIM3/TIM4/TIM5)
24 23 22
OC2M
Res. Res.
[3]
Res.
rw
8 7 6
OC1CE
IC1F[3:0]
rw rw rw
DocID024597 Rev 3
21 20 19
Res. Res. Res.
5 4 3
OC1M[2:0] OC1PE OC1FE
IC1PSC[1:0]
rw rw rw
18 17 16
OC1M
Res. Res.
[3]
Res.
rw
2 1 0
CC1S[1:0]
rw rw rw
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