ST STM32L4x6 Reference Manual page 535

RM0351
Bits 21:18 PRESC[3:0]: ADC prescaler
Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL=0,
Bits 17:16 CKMODE[1:0]: ADC clock mode
Note: Software is allowed to write these bits only when the ADCs are disabled (ADCAL=0,
Bits 15:14 MDMA[1:0]: Direct memory access mode for dual ADC mode
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
Bit 13 DMACFG: DMA configuration (for dual ADC mode)
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
Bit 12 Reserved, must be kept at reset value.
These bits are set and cleared by software to select the frequency of the clock to the ADC.
The clock is common for all the ADCs.
0000: input ADC clock not divided
0001: input ADC clock divided by 2
0010: input ADC clock divided by 4
0011: input ADC clock divided by 6
0100: input ADC clock divided by 8
0101: input ADC clock divided by 10
0110: input ADC clock divided by 12
0111: input ADC clock divided by 16
1000: input ADC clock divided by 32
1001: input ADC clock divided by 64
1010: input ADC clock divided by 128
1011: input ADC clock divided by 256
other: reserved
JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The ADC prescaler
value is applied only when CKMODE[1:0] = 0b00.
These bits are set and cleared by software to define the ADC clock scheme (which is
common to both master and slave ADCs):
00: CK_ADCx (x=123) (Asynchronous clock mode), generated at product level (refer to
Section 6: Reset and clock control
01: HCLK/1 (Synchronous clock mode). This configuration must be enabled only if the AHB
clock prescaler is set to 1 (HPRE[3:0] = 0xxx in RCC_CFGR register) and if the system clock
has a 50% duty cycle.
10: HCLK/2 (Synchronous clock mode)
11: HCLK/4 (Synchronous clock mode)
In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start
of a conversion.
JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
This bit-field is set and cleared by software. Refer to the DMA controller section for more
details.
00: MDMA mode disabled
01: reserved
10: MDMA mode enabled for 12 and 10-bit resolution
11: MDMA mode enabled for 8 and 6-bit resolution
regular conversion is ongoing).
This bit is set and cleared by software to select between two DMA modes of operation and is
effective only when DMAEN=1.
0: DMA One Shot Mode selected
1: DMA Circular Mode selected
For more details, refer to
regular conversion is ongoing).
(RCC))
Section : Managing conversions using the DMA
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