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ST STM32L0x3 Reference Manual

Ultra-low-power advanced arm-based 32-bit mcus

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RM0367

Reference manual

®

Ultra-low-power STM32L0x3 advanced Arm

-based

32-bit MCUs

Introduction

This reference manual targets application developers. It provides complete information on

how to use the STM32L0x3 microcontroller memory and peripherals.

The STM32L0x3 is a line of microcontrollers with different memory sizes, packages and

peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the

corresponding datasheets.

®

®

®

For information on the Arm

Cortex

-M0+ core, refer to the Cortex

-M0+ Technical

Reference Manual.

The STM32L0x3 microcontrollers include state-of-the-art patented technology.

Related documents

®

• Cortex

-M0+ Technical Reference Manual, available from www.arm.com.

®

• STM32L0 Series Cortex

-M0+ programming manual (PM0223).

• STM32L0x3 datasheets.

• STM32L0x3 erratasheet.

April 2021

RM0367 Rev 7

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Summary of Contents for ST STM32L0x3

Page 1 This reference manual targets application developers. It provides complete information on how to use the STM32L0x3 microcontroller memory and peripherals. The STM32L0x3 is a line of microcontrollers with different memory sizes, packages and peripherals. For ordering information, mechanical and electrical device characteristics please refer to the corresponding datasheets.
Page 2: Table Of Contents
Contents RM0367 Contents Documentation conventions ....... . . 52 General information ......... 52 List of abbreviations for registers .
Page 3 RM0367 Contents Unlocking/locking operations ........82 Detailed description of NVM write/erase operations.
Page 4 Contents RM0367 3.7.11 Flash register map ........120 Option bytes .
Page 5 RM0367 Contents Segments properties ..........134 5.3.5 Firewall initialization .
Page 6 Contents RM0367 Low-power modes ......... 153 6.3.1 Behavior of clocks in low-power modes .
Page 7 RM0367 Contents Reset ........... 173 7.1.1 System reset .
Page 8 Contents RM0367 7.3.8 GPIO reset register (RCC_IOPRSTR) ......198 7.3.9 AHB peripheral reset register (RCC_AHBRSTR) ....199 7.3.10 APB2 peripheral reset register (RCC_APB2RSTR) .
Page 9 RM0367 Contents 8.7.4 CRS interrupt flag clear register (CRS_ICR) ....235 8.7.5 CRS register map ........236 General-purpose I/Os (GPIO) .
Page 10 Contents RM0367 9.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A to E and H) ......... 251 9.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A to E and H) .
Page 11 RM0367 Contents Circular mode (in memory-to-peripheral/peripheral-to-memory transfers) ..273 Memory-to-memory mode .........273 Peripheral-to-peripheral mode .
Page 12 Contents RM0367 13.5.3 EXTI rising edge trigger selection register (EXTI_RTSR) ..298 13.5.4 Falling edge trigger selection register (EXTI_FTSR) ....299 13.5.5 EXTI software interrupt event register (EXTI_SWIER) .
Page 13 RM0367 Contents 14.5.1 Data register and data alignment (ADC_DR, ALIGN) ... . . 321 14.5.2 ADC overrun (OVR, OVRMOD) ......321 14.5.3 Managing a sequence of data converted without using the DMA .
Page 14 Contents RM0367 14.12.11 ADC common configuration register (ADC_CCR) ....350 14.13 ADC register map ......... . 351 Digital-to-analog converter (DAC) .
Page 15 RM0367 Contents 15.10.1 DAC control register (DAC_CR) ......365 15.10.2 DAC software trigger register (DAC_SWTRIGR) ....369 15.10.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) .
Page 16 Contents RM0367 Liquid crystal display controller (LCD) ......384 17.1 Introduction ..........384 Glossary .
Page 17 RM0367 Contents Touch sensing controller (TSC) ......414 18.1 Introduction ..........414 18.2 TSC main features .
Page 18 Contents RM0367 Overview............435 Typical data processing .
Page 19 RM0367 Contents 19.7.2 AES status register (AES_SR) ......460 19.7.3 AES data input register (AES_DINR) ......461 19.7.4 AES data output register (AES_DOUTR) .
Page 20 Contents RM0367 20.6.1 Introduction ..........474 20.6.2 Validation conditions .
Page 21 RM0367 Contents Slave mode: Reset mode ......... .512 Slave mode: Gated mode .
Page 22 Contents RM0367 General-purpose timers (TIM21/22) ......547 22.1 Introduction ..........547 22.2 TIM21/22 main features .
Page 23 RM0367 Contents 22.4.6 TIM21/22 event generation register (TIMx_EGR) ....591 22.4.7 TIM21/22 capture/compare mode register 1 (TIMx_CCMR1) ..592 Output compare mode .
Page 24 Contents RM0367 24.3 LPTIM implementation ........616 24.4 LPTIM functional description .
Page 25 RM0367 Contents 25.3.2 Window option ......... . . 637 Configuring the IWDG when the window option is enabled .
Page 26 Contents RM0367 27.4.2 GPIOs controlled by the RTC ....... 654 27.4.3 Clock and prescalers .
Page 27 RM0367 Contents 27.7.3 RTC control register (RTC_CR) ......671 27.7.4 RTC initialization and status register (RTC_ISR) ....674 27.7.5 RTC prescaler register (RTC_PRER) .
Page 28 Contents RM0367 Reception ............706 Transmission .
Page 29 RM0367 Contents Bus error (BERR) ..........743 Arbitration lost (ARLO) .
Page 30 Contents RM0367 Idle characters ..........773 29.5.3 USART receiver .
Page 31 RM0367 Contents 29.5.16 RS232 hardware flow control and RS485 driver enable using USART ..........802 RS232 RTS flow control .
Page 32 Contents RM0367 Start bit detection ..........839 Character reception .
Page 33 RM0367 Contents 30.7.6 Interrupt & status register (LPUART_ISR) ..... . 866 30.7.7 Interrupt flag clear register (LPUART_ICR) ..... 869 30.7.8 Receive data register (LPUART_RDR) .
Page 34 Contents RM0367 Overrun flag (OVR)..........891 Mode fault (MODF) .
Page 35 RM0367 Contents 31.7 SPI and I S registers ........913 31.7.1 SPI control register 1 (SPI_CR1) (not used in I S mode) .
Page 36 Contents RM0367 LPM control and status register (USB_LPMCSR) ..... . .944 Battery charging detector (USB_BCDR) ......945 Endpoint-specific registers .
Page 37 RM0367 Contents 33.9.3 Debug MCU configuration register (DBG_CR) ....965 33.9.4 Debug MCU APB1 freeze register (DBG_APB1_FZ) ... . . 967 33.9.5 Debug MCU APB2 freeze register (DBG_APB2_FZ) .
Page 38 Contents RM0367 A.5.2 Alternate function selection sequence code example....984 A.5.3 Analog GPIO configuration code example ..... . 984 DMA .
Page 39 RM0367 Contents A.11.4 Input capture data management code example ....996 A.11.5 PWM input configuration code example ......997 A.11.6 PWM input with DMA configuration code example .
Page 40 Contents RM0367 A.16.2 I2C slave transmitter code example ......1013 A.16.3 I2C slave receiver code example ......1013 A.16.4 I2C configured in master mode to receive code example.
Page 41 Overview of features per category ......... . . 54 Table 3. STM32L0x3 peripheral register boundary addresses ......60 Table 4.
Page 42 List of tables RM0367 Table 47. Port bit configuration table ..........239 Table 48.
Page 43 Table 139. STM32L0x3 USART/LPUART features ........
Page 44 Table 148. STM32L0x3 USART/LPUART features ........
Page 45 STM32L0x3 firewall connection schematics ........131...
Page 46 List of figures RM0367 Figure 48. Behavior with WAIT = 1, AUTOFF = 1 ........326 Figure 49.
Page 47 RM0367 List of figures Figure 100. 128-bit block construction with respect to data swap ......452 Figure 101.
Page 48 List of figures RM0367 Figure 151. Triggering timer x and y with timer x TI1 input ....... . . 521 Figure 152.
Page 49 RM0367 List of figures Figure 199. Control circuit in normal mode, internal clock divided by 1 ......609 Figure 200.
Page 50 List of figures RM0367 Figure 248. Data sampling when oversampling by 8 ........778 Figure 249.
Page 51 Figure 314. Packet buffer areas with examples of buffer description table locations ... . . 928 ® Figure 315. Block diagram of STM32L0x3 MCU and Cortex -M0+-level debug support ..956...
Page 52: Documentation Conventions
Documentation conventions RM0367 Documentation conventions General information ®(a) ® The STM32L0x3 devices have an Arm Cortex -M0+ core. List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to this bit.
Page 53: Glossary
RM0367 Documentation conventions Glossary This section gives a brief definition of acronyms and abbreviations used in this document: • Sector: 32 pages write protection granularity in the Code area • Page: 32 words for Code and System Memory areas, 1 word for Data, Factory Option and User Option areas •...
Page 54: Table 1. Stm32L0X3 Memory Density
Documentation conventions RM0367 Table 1. STM32L0x3 memory density Memory density Category 3 Category 5 16 Kbytes STM32L053x 32 Kbytes STM32L063x (AES) STM32L053x STM32L073x 64 Kbytes STM32L063x (AES) STM32L083x (AES) STM32L073x 128 Kbytes STM32L083x (AES) STM32L073x 192 Kbytes STM32L083x (AES) Table 2. Overview of features per category...
Page 55 RM0367 Documentation conventions Table 2. Overview of features per category (continued) Feature Category 3 Category 5 Liquid crystal display controller (LCD) 8x28 or 4x32 8x48 or 4x52 Touch sensing controller (TSC1) full-featured full-featured Advanced encryption standard hardware accelerator (AES) full-featured full-featured Random number generator (RNG) full-featured...
Page 56: System And Memory Overview
SPI1/2 USB SRAM USB FS DMA request MS32790V2 1. Refer to Table 1: STM32L0x3 memory density, to Table 2: Overview of features per category and to the device datasheets for the GPIO ports and peripherals available on your device. 56/1043...
Page 57: S0: Cortex®-Bus
RM0367 System and memory overview ® 2.1.1 S0: Cortex -bus ® This bus connects the DCode/ICode bus of the Cortex -M0+ core to the BusMatrix. This bus is used by the core to fetch instructions, get data and access the AHB/APB resources. 2.1.2 S1: DMA-bus This bus connects the AHB master interface of the DMA to the BusMatrix which manages...
Page 58: Memory Organization
RM0367 Memory organization 2.2.1 Introduction Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant.
Page 59: Memory Map And Register Boundary Addresses
RM0367 2.2.2 Memory map and register boundary addresses Figure 2. Memory map 0xFFFF FFFF 0x5000 1FFF IOPORT 0xE010 0000 Cortex-M0+ 0x5000 0000 peripherals 0xE000 0000 reserved 0xC000 0000 0x4002 63FF 0x4002 0000 reserved 0xA000 0000 0x4001 8000 0x1FFF FFFF Option bytes APB2 0x4001 0000 0x8000 0000...
Page 60: Table 3. Stm32L0X3 Peripheral Register Boundary Addresses
RM0367 The following table gives the boundary addresses of the peripherals available in the devices. Table 3. STM32L0x3 peripheral register boundary addresses Boundary address Size (bytes) Peripheral Peripheral register map Section 9.4.12: GPIO register 0X5000 1C00 - 0X5000 1FFF GPIOH...
Page 61 RM0367 Table 3. STM32L0x3 peripheral register boundary addresses (continued) Boundary address Size (bytes) Peripheral Peripheral register map 0X4001 5C00 - 0X4001 FFFF 42 K Reserved Section 33.10: DBG register 0X4001 5800 - 0X4001 5BFF 0X4001 3C00 - 0X4001 57FF Reserved Section 29.8.12: USART...
Page 62 RM0367 Table 3. STM32L0x3 peripheral register boundary addresses (continued) Boundary address Size (bytes) Peripheral Peripheral register map 0X4000 8000 - 0X4000 FFFF 32 K Reserved Section 24.7.9: LPTIM register 0X4000 7C00 - 0X4000 7FFF LPTIM1 Section 28.7.12: I2C register 0X4000 7800 - 0X4000 7BFF I2C3 Section 15.10.15: DAC register...
Page 63 RM0367 Table 3. STM32L0x3 peripheral register boundary addresses (continued) Boundary address Size (bytes) Peripheral Peripheral register map Section 28.7.12: I2C register 0X4000 5800 - 0X4000 5BFF I2C2 Section 28.7.12: I2C register 0X4000 5400 - 0X4000 57FF I2C1 Section 29.8.12: USART...
Page 64: Embedded Sram
(SYSCFG_CFGR1)). Boot configuration In the STM32L0x3, three different boot modes can be selected through the BOOT0 pin and boot configuration bits in the User option byte, as shown in the following table. Table 4. Boot modes Boot mode selection...
Page 65: Bank Swapping (Category 5 Devices Only)
MEM_MODE bits in the SYSCFG memory remap register (SYSCFG_CFGR1). Embedded bootloader bootloader The embedded is located in the System memory, programmed by ST during production. It is used to reprogram the Flash memory using one of the following serial interfaces: •...
Page 66: Flash Program Memory And Data Eeprom (Flash)
Flash program memory and data EEPROM (FLASH) RM0367 Flash program memory and data EEPROM (FLASH) Introduction The non-volatile memory (NVM) is composed of: • Up to 192 Kbytes of Flash program memory. This area is used to store the application code.
Page 67: Nvm Functional Description
RM0367 Flash program memory and data EEPROM (FLASH) NVM functional description 3.3.1 NVM organization The NVM is organized as 32-bit memory cells that can be used to store code, data, boot code or Option bytes. The memory array is divided into pages. A page is composed of 32 words (or 128 bytes) in Flash program memory and System memory, and 1 single word (or 4 bytes) in data EEPROM and Option bytes areas (user and factory).
Page 68: Table 6. Nvm Organization For Ufb = 0 (192 Kbyte Category 5 Devices)
Flash program memory and data EEPROM (FLASH) RM0367 Table 6. NVM organization for UFB = 0 (192 Kbyte category 5 devices) Size NVM addresses Name Description (bytes) 0x0800 0000 - 0x0800 007F 128 bytes Page 0 0x0800 0080 - 0x0800 00FF 128 bytes Page 1 sector 0...
Page 69: Table 7. Flash Memory And Data Eeprom Remapping (192 Kbyte Category 5 Devices)
RM0367 Flash program memory and data EEPROM (FLASH) Table 7. Flash memory and data EEPROM remapping (192 Kbyte category 5 devices) NVM addresses Remapped addresses MEM_MODE = 0, MEM_MODE = 0, MEM_MODE = 0, MEM_MODE = 0, Description BOOT0= 0 and BOOT0= 0 and BOOT0= 0 and BOOT0= 0 and...
Page 70: Table 9. Flash Memory And Data Eeprom Remapping (128 Kbyte Category 5 Devices)
Flash program memory and data EEPROM (FLASH) RM0367 Table 8. NVM organization for UFB = 0 (128 Kbyte category 5 devices) (continued) NVM addresses Size (bytes) Name Description 0x1FF0 0000 - 0x1FF0 1FFF 8 Kbytes System memory Information block 0x1FF8 0020 - 0x1FF8 007F 96 bytes Factory Options 0x1FF8 0000 - 0x1FF8 001F...
Page 71: Dual-Bank Boot Capability
RM0367 Flash program memory and data EEPROM (FLASH) 3.3.2 Dual-bank boot capability Category 5 devices have two Flash memory banks: Bank 1 and Bank 2. They feature an additional boot mechanism which allows booting either from Bank 2 or from Bank 1 depending on BFB2 bit status (bit 23 in FLASH_OPTR register).
Page 72: Reading The Nvm
Flash program memory and data EEPROM (FLASH) RM0367 Table 11. Boot pin and BFB2 bit configuration (continued) Boot mode selection Protection BFB2 Boot mode Aliasing nBOOT1 level BOOT0 option User Flash memory User Flash memory Bank1 is selected as the User Flash memory boot area.
Page 73: Relation Between Cpu Frequency/Operation Mode/Nvm Read Time
RM0367 Flash program memory and data EEPROM (FLASH) You can read the NVM by word (4 bytes), half-word (2 bytes) or byte. When the NVM features only one bank, it is not possible to read the NVM during a write/erase operation. If a write/erase operation is ongoing, the reading will be in a wait state until the write/erase operation completes, stalling the master that requested the read operation, except when the address is read-protected.
Page 74 Flash program memory and data EEPROM (FLASH) RM0367 Change the CPU Frequency After reset, the clock used is the MSI (2.1 MHz) and 0 wait state is configured in the FLASH_ACR register. The following software sequences have to be respected to tune the number of wait states needed to access the NVM with the CPU frequency.
Page 75: Data Buffering
RM0367 Flash program memory and data EEPROM (FLASH) Data buffering In the NVM, six buffers can impact the performance (and in some conditions help to reduce the power consumption) during read operations, both for fetch and data. The structure of one buffer is shown on Figure Figure 3.
Page 76: Table 14. Internal Buffer Management
Flash program memory and data EEPROM (FLASH) RM0367 Table 14. Internal buffer management Buffers for fetch Buffers for data DISAB_BUF PREFTEN PRE_READ Buffers for Buffers for Buffers for Buffers for Buffers for jumps prefetch last value pre-read last value If a value in a buffer is not empty, the history shows the time elapsed between the moment it has been read or written.
Page 77: Figure 4. Timing To Fetch And Execute Instructions With Prefetch Disabled
RM0367 Flash program memory and data EEPROM (FLASH) To manage the fetch, the memory interface uses 4 buffers: at reset (DISAB_BUF = 0, PRFTEN = 0, PRE_READ = 0). 3 buffers are used to manage the jumps and 1 buffer to store the last value fetched.
Page 78 Flash program memory and data EEPROM (FLASH) RM0367 Figure 5 shows the timing to fetch and execute instructions from the NVM with 0 wait states (a) and 1 wait state (b) when the prefetch is enabled. The read executed by the prefetch appears in green.
Page 79: Table 15. Configurations For Buffers And Speculative Reading
RM0367 Flash program memory and data EEPROM (FLASH) Figure 5. Timing to fetch and execute instructions with prefetch enabled cycle cycle cycle cycle cycle cycle cycle cycle cycle Addr Fetch Exec. Exec. 1 & 2 1 & 2 Addr Fetch Exec.
Page 80: Table 16. Dhrystone Performances In All Memory Interface Configurations
Flash program memory and data EEPROM (FLASH) RM0367 Dhrystone performances The Dhrystone test is used to evaluate the memory interface performances. The test has been executed in all memory interface configurations. Refer to Table 16 for a summary of the results. Common parameters are: •...
Page 81: Writing/Erasing The Nvm
RM0367 Flash program memory and data EEPROM (FLASH) 3.3.4 Writing/erasing the NVM There are many ways to change the NVM content. The memory interface helps to reduce the possibility of unwanted changes and to implement by hardware all sequences necessary to erase or write in the different memory areas.
Page 82: Unlocking/Locking Operations
Flash program memory and data EEPROM (FLASH) RM0367 When the memory interface receives the first address, it stalls the master for some pulses of clock while it checks the protections and the previous value and it latches the new value inside the NVM (for more details, see Table 17).
Page 83 RM0367 Flash program memory and data EEPROM (FLASH) Any wrong key sequence will lock up FLASH_PECR until the next reset and generate a hard fault. Idem if the master tries to write another register between the two key sequences or if it uses the wrong key. A reading access does not generate an error and does not interrupt the sequence.
Page 84 Flash program memory and data EEPROM (FLASH) RM0367 To lock the Flash program memory again, the software only needs to set PRGLOCK bit in FLASH_PECR. When locked again, PRGLOCK bit needs a new sequence to return to 0. If PELOCK returns to 1 (locked), PRGLOCK is automatically locked, too. Unlocking the Option bytes area An additional write protection is implemented on the Option bytes area.
Page 85: Detailed Description Of Nvm Write/Erase Operations
RM0367 Flash program memory and data EEPROM (FLASH) Detailed description of NVM write/erase operations This section details the different types of write and erase operations, showing the necessary bits for each one. Write to data EEPROM • Purpose Write one word in the data EEPROM with a specific value. •...
Page 86 Flash program memory and data EEPROM (FLASH) RM0367 Erase data EEPROM • Purpose Delete one row in data EEPROM. This operation performs the same function as Write a word which size is null to data EEPROM. It is available for compatibility purpose only. •...
Page 87 RM0367 Flash program memory and data EEPROM (FLASH) This operation aims at writing a word in the Option bytes area. The Option bytes area can only be written in Level 0 or Level 1. The user must consider that, in a word, the 16 higher bits (from 16 to 31) have to be the complement of the 16 lower bits (from 0 to 15): a mismatch between the higher and lower parts of data would generate an error during the Option bytes loading (see Section 3.8: Option...
Page 88 Flash program memory and data EEPROM (FLASH) RM0367 Erase Option bytes • Purpose Delete one row in the Option bytes area. This operation performs the same function as Write Option Byte with a zero value. It is available for compatibility purpose only. •...
Page 89 RM0367 Flash program memory and data EEPROM (FLASH) Program a single word to Flash program memory • Purpose Write one word in the Flash program memory with a specific value. • Size Write only by word. • Address Select an address in the Flash program memory. •...
Page 90 Flash program memory and data EEPROM (FLASH) RM0367 Program half-page in Flash program memory • Purpose Write one half page (16 words) in the Flash program memory. • Size Write only by word. • Address Select one address in the Flash program memory aligned to a half-page (for the first address) and inside the same half-page selected by the second address for the next 15 addresses.
Page 91: Parallel Write Half-Page Flash Program Memory
RM0367 Flash program memory and data EEPROM (FLASH) – Other categories NOTZEROERR is set to 1. Writing a word to an address containing a non-null value is not performed. When a half-page operation starts, the memory interface waits for 16 addresses/data, aborting (with a hard fault) all read accesses that are not a fetch (refer to Fetch and prefetch).
Page 92 Flash program memory and data EEPROM (FLASH) RM0367 Erase a page in Flash program memory • Purpose Delete one page (32 words) in the Flash program memory. • Size Erase only by word (it deletes a page of the Flash program memory writing with a word size) •...
Page 93 RM0367 Flash program memory and data EEPROM (FLASH) Mass erase • Purpose Remove the read and write protection on the Flash program memory and data EEPROM. • Size Erase only by word. • Address To generate a mass erase, it is necessary to write 0x015500AA to the first Option bytes address (bits 31 to 25 and 15 to 9 are not complemented because they are not used, and not checked) with Level 1 as the actual level.
Page 94: Table 17. Nvm Write/Erase Timings
Flash program memory and data EEPROM (FLASH) RM0367 Timing tables Table 17. NVM write/erase timings Delay to latch the first Delay to latch the next Operation address/data address/data (in AHB clock pulses) (in AHB clock pulses) Write to data EEPROM Erase data EEPROM Write Option bytes Erase Option bytes...
Page 95: Status Register
RM0367 Flash program memory and data EEPROM (FLASH) Status register The FLASH_SR Status Register gives some information on the memory interface or the NVM status (operation(s) ongoing) and about errors that happened. This flags is set and reset by hardware. It is set to 1 every time the memory interface executes a write/erase operation, and it informs that no other operation can be executed.
Page 96: Memory Protection
Flash program memory and data EEPROM (FLASH) RM0367 To reset this flag, the software need to write it to 1. SIZERR This flag is set by hardware and reset by software. It informs when a size error happened. It is raised when: •...
Page 97: Rdp (Read Out Protection)
RM0367 Flash program memory and data EEPROM (FLASH) Three types of protections are implemented. 3.4.1 RDP (Read Out Protection) This type of protection aims at protecting against unwanted read (hacking) of the NVM content. This protection is managed by RDPROT bitfield in the FLASH_OPTR register. The value is loaded from the Option bytes area during a boot and copied in the read-only register.
Page 98: Pcrop (Proprietary Code Read-Out Protection)
Flash program memory and data EEPROM (FLASH) RM0367 Figure 6. RDP levels Write Level 1 RDP = 0xCC RDP /= 0xAA RDP /= 0xCC Write (default) RDP = 0xAA Write Mass erase RDP /= 0xCC and RDP /= 0xAA Write RDP /= 0xAA and RDP /= 0xCC Level 2...
Page 99: Table 20. Link Between Protection Bits Of Flash_Wrprotx Register And Protected Address In Flash Program Memory
RM0367 Flash program memory and data EEPROM (FLASH) Any read access performed as data (see Read as data and pre-read) in a protected sector will trigger the RDERR flag in the FLASH_SR register. Any read-protected sector is also write-protected and any write access to one of these sectors will trigger the WRPERR flag in the FLASH_SR register.
Page 100: Protections Against Unwanted Write/Erase Operations
Flash program memory and data EEPROM (FLASH) RM0367 The only way to remove a protection from a sector is to request a mass erase (which changes the protection level to 0 and disables PcROP): when PcROP is disabled, the protection on sectors can be changed freely. 3.4.3 Protections against unwanted write/erase operations The memory interface implements two ways to protect against unwanted write/erase...
Page 101: Write/Erase Protection Management
RM0367 Flash program memory and data EEPROM (FLASH) Table 21. Memory access vs mode, protection and Flash program memory sectors (continued) Mode User (including In Application User Flash program memory Programming) in Debug, or sectors no Debug, or with Boot in RAM, or no Boot in RAM, or with Boot in System memory no Boot in System memory...
Page 102: Protection Errors
Flash program memory and data EEPROM (FLASH) RM0367 3.4.5 Protection errors Write protection error flag (WRPERR) If an erase/program operation to a write-protected page of the Flash program memory and data EEPROM is launched, the Write Protection Error flag (WRPERR) is set in the FLASH_SR register.
Page 103: Hard Fault
RM0367 Flash program memory and data EEPROM (FLASH) Table 22. Flash interrupt request Interrupt event Event flag Enable control bit End of operation EOPIE RDERR WRPERR PGAERR Error OPTVERR ERRIE SIZERR FWWERR NOTZEROERR 3.5.1 Hard fault A hard fault is generated on: •...
Page 104: Option Byte Loading
Flash program memory and data EEPROM (FLASH) RM0367 master are blocked, the memory interface continues the operation freeing the bus and the master. • If the address is protected, the write/erase is filtered (the write/erase requested is never sent to the memory) and an error is raised. •...
Page 105: Write While Another Write Operation Is Ongoing
RM0367 Flash program memory and data EEPROM (FLASH) Write while another write operation is ongoing If the master requests a write operation while another one is ongoing, there are different cases: • If the previous write uses a Single programming operation or a Multiple programming operation (half page)
Page 106: Flash Register Description
Flash program memory and data EEPROM (FLASH) RM0367 Flash register description Read registers To read all internal registers of the memory interface, the user must read at the register addresses. The content is available immediately (no wait state is necessary to read registers).
Page 107: Access Control Register (Flash_Acr)
RM0367 Flash program memory and data EEPROM (FLASH) 3.7.1 Access control register (FLASH_ACR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 108: Program And Erase Control Register (Flash_Pecr)
Flash program memory and data EEPROM (FLASH) RM0367 Bit 2 Reserved, must be kept at reset value Bit 1 PRFTEN This bit enables the prefetch. It is automatically reset every time the DISAB_BUF bit (in this register) is set to 1. To know how the prefetch works, see the Fetch and prefetch section.
Page 109 RM0367 Flash program memory and data EEPROM (FLASH) Bits 31:24 Reserved, must be kept at reset value Bit 23 NZDISABLE: Non-Zero check notification disable When this bit is set, the application software does not check if the previous NVM content is zero before programming a word or an half-page in the program or boot area.
Page 110 Flash program memory and data EEPROM (FLASH) RM0367 Bit 8 FIX 0: An erase phase is automatically performed, when necessary, before a program operation in the data EEPROM and the Option bytes areas. The programming time can be: Tprog (program operation) or 2 * Tprog (erase + program operations). 1: The program operation is always performed with a preliminary erase and the programming time is: 2 * Tprog.
Page 111 RM0367 Flash program memory and data EEPROM (FLASH) Bit 2 OPTLOCK: Option bytes lock This bit blocks the write/erase operations to the user Option bytes area and the OBL_LAUNCH bit (in this register). It can only be written to 1 to re-lock. To reset to 0, a correct sequence of unlock with OPTKEYR register is necessary (see Unlocking the Option bytes area), with PELOCK bit at 0.
Page 112: Power-Down Key Register (Flash_Pdkeyr)
Flash program memory and data EEPROM (FLASH) RM0367 3.7.3 Power-down key register (FLASH_PDKEYR) Address offset: 0x08 Reset value: 0x0000 0000 FLASH_PDKEYR[31:16] FLASH_PDKEYR15:0] Bits 31:0 This is a write-only register. With a sequence of two write operations (the first one with 0x04152637 and the second one with 0xFAFBFCFD), the write size being that of a word, it is possible to unlock the RUN_PD bit of the FLASH_ACR register.
Page 113: Option Bytes Unlock Key Register (Flash_Optkeyr)
RM0367 Flash program memory and data EEPROM (FLASH) 3.7.6 Option bytes unlock key register (FLASH_OPTKEYR) Address offset: 0x14 Reset value: 0x0000 0000 FLASH_OPTKEYR[31:16] FLASH_OPTKEYR[15:0] Bits 31:0 This is a write-only register. With a sequence of two write operations (the first one with 0xFBEAD9C8 and the second one with 0x24252627), the write size being that of a word, it is possible to unlock the Option bytes area and the OBL_LAUNCH bit.
Page 114: Status Register (Flash_Sr)
Flash program memory and data EEPROM (FLASH) RM0367 3.7.7 Status register (FLASH_SR) Address offset: 0x018 Reset value: 0x0000 000C Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rc_w1 rc_w1 Res. Res. Res. Res. Res. Res.
Page 115 RM0367 Flash program memory and data EEPROM (FLASH) Bit 10 SIZERR: Size error This bit is set by hardware when the size of data to program is not correct. It is cleared by writing 1. 0: No size error happened. 1: One size error happened.
Page 116: Option Bytes Register (Flash_Optr)
Flash program memory and data EEPROM (FLASH) RM0367 3.7.8 Option bytes register (FLASH_OPTR) Address offset 0x1C Reset value: 0xX0XX 0XXX. It depends on the value programmed in the option bytes. During production, it is set to 0x8070 00AA. Res. Res. Res.
Page 117 RM0367 Flash program memory and data EEPROM (FLASH) Bit 20 WDG_SW If there is a mismatch on this configuration during the Option bytes loading, it is loaded with 1. 0: Hardware watchdog. 1: Software watchdog. Bits 19:16 BOR_LEV: Brownout reset threshold level These bits reset the threshold level for a 1.45 V to 1.55 V voltage range (power-down only).
Page 118: Write Protection Register 1 (Flash_Wrprot1)
Flash program memory and data EEPROM (FLASH) RM0367 3.7.9 Write protection register 1 (FLASH_WRPROT1) Address offset: 0x20 Reset value: 0xXXXX XXXX. It depends on the value programmed in the option bytes. During production, it is set to 0x0000 0000. WRPROT1[31:16] WRPROT1[15:0] Bits 31:0 WRPROT1: Write protection –...
Page 119: Write Protection Register 2 (Flash_Wrprot2)
RM0367 Flash program memory and data EEPROM (FLASH) 3.7.10 Write protection register 2 (FLASH_WRPROT2) Address offset: 0x80 Reset value: 0x 0000 XXXX. It depends on the value programmed in the option bytes. During production, it is set to 0x0000 0000. Res.
Page 120: Flash Register Map
Flash program memory and data EEPROM (FLASH) RM0367 3.7.11 Flash register map Table 23. Flash interface - register map and reset values Off- Register FLASH_ACR 0x00 0x00000000 FLASH_PECR 0x004 0x00000007 FLASH_ PDKEYR[31:0] PDKEYR 0x008 0x00000000 FLASH_ PKEYR[31:0] PKEYR 0x00C 0x00000000 FLASH_ PRGKEYR[31:0] PRGKEYR...
Page 121: Option Bytes
RM0367 Flash program memory and data EEPROM (FLASH) Option bytes On the NVM, an area is reserved to store a set of Option bytes which are used to configure the product. Some option bytes are written in factory while others can be configured by the end user.
Page 122: Mismatch When Loading Protection Flags
Flash program memory and data EEPROM (FLASH) RM0367 3.8.2 Mismatch when loading protection flags When there is a mismatch during an Option byte loading, the memory interface sets the default value in registers. In the Option byte area, there are three kinds of protection information: •...
Page 123: Cyclic Redundancy Check Calculation Unit (Crc)
RM0367 Cyclic redundancy check calculation unit (CRC) Cyclic redundancy check calculation unit (CRC) Introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16- or 32-bit data word and a generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity.
Page 124: Crc Functional Description
Cyclic redundancy check calculation unit (CRC) RM0367 CRC functional description 4.3.1 CRC block diagram Figure 7. CRC calculation unit block diagram 32-bit AHB bus 32-bit (read access) Data register (output) crc_hclk CRC computation 32-bit (write access) Data register (input) MS19882V2 4.3.2 CRC internal signals Table 26.
Page 125: Polynomial Programmability
RM0367 Cyclic redundancy check calculation unit (CRC) The input data can be reversed, to manage the various endianness schemes. The reversing operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits in the CRC_CR register. For example: input data 0x1A2B3C4D is used for CRC calculation as: •...
Page 126: Crc Registers
Cyclic redundancy check calculation unit (CRC) RM0367 CRC registers 4.4.1 CRC data register (CRC_DR) Address offset: 0x00 Reset value: 0xFFFF FFFF DR[31:16] DR[15:0] Bits 31:0 DR[31:0]: Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read.
Page 127: Crc Control Register (Crc_Cr)
RM0367 Cyclic redundancy check calculation unit (CRC) 4.4.3 CRC control register (CRC_CR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. REV_ Res. Res. Res. Res. Res.
Page 128: Crc Initial Value (Crc_Init)
Cyclic redundancy check calculation unit (CRC) RM0367 4.4.4 CRC initial value (CRC_INIT) Address offset: 0x10 Reset value: 0xFFFF FFFF CRC_INIT[31:16] CRC_INIT[15:0] Bits 31:0 CRC_INIT[31:0]: Programmable initial CRC value This register is used to write the CRC initial value. 4.4.5 CRC polynomial (CRC_POL) Address offset: 0x14 Reset value: 0x04C1 1DB7 POL[31:16]...
Page 129: Crc Register Map
RM0367 Cyclic redundancy check calculation unit (CRC) 4.4.6 CRC register map Table 27. CRC register map and reset values Register Offset name CRC_DR DR[31:0] 0x00 Reset value CRC_IDR IDR[7:0] 0x04 Reset value CRC_CR 0x08 Reset value CRC_INIT CRC_INIT[31:0] 0x10 Reset value CRC_POL POL[31:0] 0x14...
Page 130: Firewall (Fw)
Firewall (FW) RM0367 Firewall (FW) Introduction The Firewall is made to protect a specific part of code or data into the Non-Volatile Memory, and/or to protect the Volatile data into the SRAM from the rest of the code executed outside the protected area.
Page 131: Firewall Functional Description
Firewall AMBA bus snoop The Firewall peripheral is snooping the AMBA buses on which the memories (volatile and non-volatile) are connected. A global architecture view is illustrated in Figure Figure 8. STM32L0x3 firewall connection schematics AHB Slave AHB Master 1 Flash program...
Page 132: Write Protection
Firewall (FW) RM0367 Write protection In order to offer a maximum security level, the following points need to be respected: • It is mandatory to keep a write protection on the part of the code enabling the Firewall. This activation code should be located outside the segments protected by the Firewall. •...
Page 133: Volatile Data Segment
RM0367 Firewall (FW) Volatile data segment Volatile data used by the protected code located into the code segment must be defined into the SRAM memory. The access to this segment is defined into the Section 5.3.4: Segment accesses and properties. Depending on the Volatile data segment configuration, the Firewall must be opened or not before accessing this segment area.
Page 134: Segments Properties
Firewall (FW) RM0367 The Volatile data segment is a bit different from the two others. The segment can be: • Shared (VDS bit in the register) It means that the area and the data located into this segment can be shared between the protected code and the user code executed in a non-protected area.
Page 135: Firewall States
RM0367 Firewall (FW) Below is the initialization procedure to follow: Configure the RCC to enable the clock to the Firewall module Configure the RCC to enable the clock of the system configuration registers Set the base address and length of each segment (CSSA, CSL, NVDSSA, NVDSL, VDSSA, VDSL registers) Set the configuration register of the Firewall (FW_CR register) Enable the Firewall clearing the FWDIS bit in the system configuration register.
Page 136: Opening The Firewall
Firewall (FW) RM0367 Opening the Firewall As soon as the Firewall is enabled, it is closed. It means that most of the accesses to the protected segments are forbidden (refer to Section 5.3.4: Segment accesses and properties). In order to open the Firewall to interact with the protected segments, it is mandatory to apply the “call gate”...
Page 137: Firewall Registers
RM0367 Firewall (FW) Firewall registers 5.4.1 Code segment start address (FW_CSSA) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. ADD[23:16] ADD[15:8] Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:24 Reserved, must be kept at reset value. Bits 23:8 ADD[23:8]: code segment start address The LSB bits of the start address (bit 7:0) are reserved and forced to 0 in order to allow a 256-byte granularity.
Page 138: Non-Volatile Data Segment Start Address (Fw_Nvdssa)
Firewall (FW) RM0367 5.4.3 Non-volatile data segment start address (FW_NVDSSA) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. ADD[23:16] ADD[15:8] Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:24 Reserved, must be kept at the reset value. Bits 23:8 ADD[23:8]: Non-volatile data segment start address The LSB bits of the start address (bit 7:0) are reserved and forced to 0 in order to allow a 256-byte granularity.
Page 139: Volatile Data Segment Start Address (Fw_Vdssa)
RM0367 Firewall (FW) 5.4.5 Volatile data segment start address (FW_VDSSA) Address offset: 0x10 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ADD[15:6] Res. Res. Res. Res. Res. Res. Bits 31:16 Reserved, must be kept at the reset value.
Page 140: Configuration Register (Fw_Cr)
Firewall (FW) RM0367 5.4.7 Configuration register (FW_CR) Address offset: 0x20 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 141: Firewall Register Map
RM0367 Firewall (FW) 5.4.8 Firewall register map The table below provides the Firewall register map and reset values. Table 30. Firewall register map and reset values Offset Register FW_CSSA Reset Value FW_CSL LENG Reset Value FW_NVDSSA Reset Value FW_NVDSL LENG Reset Value FW_VDSSA 0x10...
Page 142: Power Control (Pwr)
Power control (PWR) RM0367 Power control (PWR) Power supplies The device requires a 1.8-to-3.6 V V operating voltage supply (down to 1.65 V at power- down) when the BOR is available. The device requires a 1.65-to-3.6 V V operating voltage supply when the BOR is not available. An embedded linear voltage regulator is used to supply the internal digital power, ranging from 1.2 to 1.8 V.
Page 143: Independent A/D And Dac Converter Supply And Reference Voltage
RM0367 Power control (PWR) Figure 10. Power supply overview VDDA domain (from 1.65 V up to VDDA) VREF+ Temp. sensor (VDD) VDDA Reset block (VSS) VSSA VCore domain VDD domain Flash memory IO supply Standby circuitry Core (Wakeup logic, Memories IWDG, RTC, Digital LSE crystal...
Page 144: Independent Lcd Supply
Power control (PWR) RM0367 6.1.2 Independent LCD supply The V pin is provided to control the contrast of the glass LCD. This pin can be used in two ways: • It can receive from an external circuitry the desired maximum voltage that is provided on segment and common lines to the glass LCD by the microcontroller.
Page 145: Voltage Regulator
RM0367 Power control (PWR) 6.1.4 Voltage regulator An embedded linear voltage regulator supplies all the digital circuitries except for the Standby circuitry. The regulator output voltage (V ) can be programmed by software to CORE three different ranges within 1.2 - 1.8 V (typical) (see Section 6.1.5).
Page 146: Range 2 And 3
Power control (PWR) RM0367 Range 2 and 3 The regulator can also be programmed to output a regulated 1.5 V (typical, range 2) or a 1.2 V (typical, range 3) without any limitations on V (1.65 to 3.6 V). • At 1.5 V, the Flash memory is still functional but with medium read access time.
Page 147: Dynamic Voltage Scaling Configuration
RM0367 Power control (PWR) 6.1.6 Dynamic voltage scaling configuration The following sequence is required to program the voltage regulator ranges: Check V to identify which ranges are allowed (see Figure 11: Performance versus VDD and VCORE range). Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0. Configure the voltage scaling range by setting the VOS[1:0] bits in the PWR_CR register.
Page 148: Voltage Range And Limitations When Vdd Ranges From 1.71 V To 2.0 V
Voltage range and limitations when V ranges from 1.71 V to 2.0 V The STM32L0x3 voltage regulator is based on an architecture designed for Ultra-low-power a. It does not use any external capacitor. Such regulator is sensitive to fast changes of load.
Page 149: Figure 12. Power Supply Supervisors
RM0367 Power control (PWR) Figure 12. Power supply supervisors DD A 100 mV hysteresis 100 mV BO R hysteresis IT enabled PVD output BOR reset (NRST) BOR/PDR reset (NRST) POR/PDR reset (NRST) BOR always active BOR disabled by option byte POR/PDR (BOR not available) ai17211b 1.
Page 150: Power-On Reset (Por)/Power-Down Reset (Pdr)
Power control (PWR) RM0367 6.2.1 Power-on reset (POR)/power-down reset (PDR) The device has an integrated POR/PDR circuitry that allows operation down to 1.5 V. During power-on, the device remains in Reset mode when V is below a specified threshold, V , without the need for an external reset circuit.
Page 151: Programmable Voltage Detector (Pvd)
RM0367 Power control (PWR) And when the BOR option is disabled by option byte, the power-down reset is controlled by the PDR and a “gray zone” exists between the 1.65 V and V is configured through device option bytes. By default, the Level 4 threshold is activated.
Page 152: Internal Voltage Reference (Vrefint)
Power control (PWR) RM0367 generated when V drops below the PVD threshold. As an example the service routine could perform emergency shutdown tasks. Figure 15. PVD thresholds VDD/VDDA 100mV PVD threshold hysteresis PVD output MSv32795V2 6.2.4 Internal voltage reference (V REFINT The internal reference (V ) provides stable voltage for analog peripherals.
Page 153: Low-Power Modes
RM0367 Power control (PWR) Low-power modes By default, the microcontroller is in Run mode after a system or a power-on reset. In Run mode the CPU is clocked by HCLK and the program code is executed. Several low-power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event.
Page 154: Behavior Of Clocks In Low-Power Modes
Power control (PWR) RM0367 Table 32. Summary of low-power modes (continued) Effect on V Effect on V CORE Mode name Entry Wakeup domain Voltage regulator domain clocks clocks PDDS, LPSDSR Any EXTI line bits + (configured in the EXTI In low-power Stop SLEEPDEEP bit + registers, internal and...
Page 155: Slowing Down System Clocks
RM0367 Power control (PWR) 6.3.2 Slowing down system clocks In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down peripherals before entering Sleep mode. For more details refer to Section 7.3.4: Clock configuration register (RCC_CFGR).
Page 156: Exiting Low-Power Run Mode
Power control (PWR) RM0367 Exiting Low-power run mode To exit Low-power run mode proceed as follows: The regulator is forced in Main regulator mode by software. The Flash memory is switched on, if needed. The frequency of the clock system can be increased. 6.3.5 Entering low-power mode Low-power modes (except for Low-power run mode) are entered by executing the WFI...
Page 157: Sleep Mode
RM0367 Power control (PWR) 6.3.7 Sleep mode I/O states in Sleep mode In Sleep mode, all I/O pins keep the same state as in Run mode. Entering Sleep mode The Sleep mode is entered according to Section 6.3.5: Entering low-power mode.
Page 158: Low-Power Sleep Mode (Lp Sleep)
Power control (PWR) RM0367 Table 34. Sleep-on-exit Sleep-on-exit Description WFI (wait for interrupt) while: – SLEEPDEEP = 0 and – No interrupt (for WFI) or event (for WFE) is pending ® Refer to the Cortex -M0+ System Control register (see PM0223 programming manual).
Page 159: Exiting Low-Power Sleep Mode
RM0367 Power control (PWR) Note: To be able to read the RTC calendar register when the APB1 clock frequency is less than seven times the RTC clock frequency (7*RTCLCK), the software must read the calendar time and date registers twice. If the second read of the RTC_TR gives the same result as the first read, this ensures that the data is correct.
Page 160: Stop Mode
Power control (PWR) RM0367 Table 36. Sleep-on-exit (Low-power sleep) Sleep-on-exit Description WFI (wait for interrupt) while: – SLEEPDEEP = 0 and – No interrupt (for WFI) or event (for WFE) is pending ® Refer to the Cortex -M0+ System Control register (see PM0223 programming manual).
Page 161: Exiting Stop Mode
RM0367 Power control (PWR) To further reduce power consumption in Stop mode, the internal voltage regulator can be put in low-power mode. This is configured by the LPSDSR bit in the PWR_CR register (see Section 6.4.1). The internal voltage regulator can also be kept in Main mode but the consumption will be much higher.
Page 162: Table 37. Stop Mode
Power control (PWR) RM0367 Table 37. Stop mode Stop mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – No interrupt (for WFI) or event (for WFE) is pending. ® – SLEEPDEEP bit is set in Cortex -M0+ System Control register –...
Page 163: Standby Mode
RM0367 Power control (PWR) 6.3.10 Standby mode The Standby mode allows to achieve the lowest power consumption. It is based on the ® Cortex -M0+ Deepsleep mode, with the voltage regulator disabled. The V domain is CORE consequently powered off. The PLL, the MSI, the HSI16 oscillator and the HSE oscillator are also switched off.
Page 164: Debug Mode
Power control (PWR) RM0367 Table 38. Standby mode Standby mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: ® – SLEEPDEEP = 1 in Cortex -M0+ System Control register – PDDS = 1 bit in Power Control register (PWR_CR) –...
Page 165: Rtc Auto-Wakeup (Awu) From The Stop Mode
RM0367 Power control (PWR) The RTC provides a programmable time base for waking up from Stop or Standby mode at regular intervals. For this purpose, two of the three alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the RCC_CSR register (see Section 7.3.21): •...
Page 166: Comparator Auto-Wakeup (Awu) From The Stop Mode
Power control (PWR) RM0367 Comparator auto-wakeup (AWU) from the Stop mode • To wake up from the Stop mode with a comparator 1 or comparator 2 wakeup event, it is necessary to: Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2 (Interrupt or Event mode) to be sensitive to the selected edges (falling, rising or falling and rising) Configure the comparator to generate the event.
Page 167: Power Control Registers
RM0367 Power control (PWR) Power control registers The peripheral registers have to be accessed by half-words (16-bit) or words (32-bit). 6.4.1 PWR power control register (PWR_CR) Address offset: 0x00 Reset value: 0x0000 1000 (reset by wakeup from Standby mode) Res. Res.
Page 168 Power control (PWR) RM0367 Bit 10 FWU: Fast wakeup This bit works in conjunction with ULP bit. If ULP = 0, FWU is ignored If ULP = 1 and FWU = 1: V startup time is ignored when exiting from low-power mode. REFINT The VREFINTRDYF flag in the PWR_CSR register indicates when the V is ready...
Page 169 RM0367 Power control (PWR) Bit 2 CWUF: Clear wakeup flag This bit is always read as 0. 0: No effect 1: Clear the WUF Wakeup flag after 2 system clock cycles Bit 1 PDDS: Power-down deepsleep This bit is set and cleared by software. 0: Enter Stop mode when the CPU enters Deepsleep.
Page 170: Pwr Power Control/Status Register (Pwr_Csr)
Power control (PWR) RM0367 6.4.2 PWR power control/status register (PWR_CSR) Address offset: 0x04 Reset value: 0x0000 0008 (not reset by wakeup from Standby mode) Additional APB cycles are needed to read this register versus a standard APB read. Res. Res. Res.
Page 171 RM0367 Power control (PWR) Bit 4 VOSF: Voltage Scaling select flag A delay is required for the internal regulator to be ready after the voltage range is changed. The VOSF bit indicates that the regulator has reached the voltage level defined with bits VOS of PWR_CR register.
Page 172: Pwr Register Map
Power control (PWR) RM0367 6.4.3 PWR register map The following table summarizes the PWR registers. Table 39. PWR - register map and reset values Offset Register PWR_CR PLS[2:0] [1:0] 0x000 Reset value PWR_CSR 0x004 Reset value Refer to Section 2.2 on page 58 for the register boundary addresses.
Page 173: Reset And Clock Control (Rcc)
RM0367 Reset and clock control (RCC) Reset and clock control (RCC) Reset There are three types of reset, defined as system reset, power reset and RTC domain reset. 7.1.1 System reset A system reset sets all registers to their reset values unless specified otherwise in the register description.
Page 174: Power Reset
Reset and clock control (RCC) RM0367 7.1.2 Power reset A power reset is generated when one of the following events occurs: • Power-on/power-down reset (POR/PDR reset) • BOR reset A power reset sets all registers to their reset values including for the RTC domain (see Figure These sources act on the NRST pin and it is always kept low during the delay phase.
Page 175: Clocks
RM0367 Reset and clock control (RCC) Clocks Four different clock sources can be used to drive the system clock (SYSCLK): • HSI16 (high-speed internal) oscillator clock • HSE (high-speed external) oscillator clock • PLL clock • MSI (multispeed internal) oscillator clock The MSI at 2.1MHz is used as system clock source after startup from power reset, system or RTC domain reset, and after wake-up from Standby mode.
Page 176 Reset and clock control (RCC) RM0367 – LSI clock – APB clock (PCLK) • The RTC/LCD clock which is derived from the following clock sources: – LSE clock, – LSI clock, – 4 MHz HSE_RTC (HSE divided by a programmable prescaler). •...
Page 177: Figure 17. Clock Tree
RM0367 Reset and clock control (RCC) Figure 17. Clock tree @V33 Enable Watchdog Legend: Watchdog LS LSI RC LSI tempo HSE = High-speed external clock signal HSI = High-speed internal clock signal RTCSEL LSI = Low-speed internal clock signal RTC2 enable LSE = Low-speed external clock signal MSI = Multispeed internal clock signal LSE OSC...
Page 178: Hse Clock
Reset and clock control (RCC) RM0367 The timer clock frequencies are automatically fixed by hardware. There are two cases: If the APB prescaler is 1, the timer clock frequencies are set to the same frequency as that of the APB domain to which the timers are connected. Otherwise, they are set to twice (×2) the frequency of the APB domain to which the timers are connected.
Page 179: External Source (Hse Bypass)
Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at an ambient temperature, T , of 25 °C.
Page 180: Msi Clock
Calibration The MSI RC oscillator frequency can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at an ambient temperature, T , of 25 °C.
Page 181: Pll
RM0367 Reset and clock control (RCC) ENREF_HSI48 in Section 10.2.3: Reference control and status register (SYSCFG_CFGR3)) The HSI48RDY flag in the Clock recovery RC register (RCC_CRRCR) indicates whether the HSI48 RC is stable or not. At startup, the HSI48 RC output clock is not released until this bit is set by hardware.
Page 182: Lse Clock
Reset and clock control (RCC) RM0367 7.2.6 LSE clock The LSE crystal is a 32.768 kHz low speed external crystal or ceramic resonator. It has the advantage of providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions.
Page 183: System Clock (Sysclk) Selection
RM0367 Reset and clock control (RCC) 7.2.8 System clock (SYSCLK) selection Four different clock sources can be used to drive the system clock (SYSCLK): • The HSI16 oscillator • The HSE oscillator • The PLL • The MSI oscillator clock (default after reset) When a clock source is used directly or through the PLL as system clock, it is not possible to stop it.
Page 184: Lse Clock Security System
Reset and clock control (RCC) RM0367 If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is used as PLL input clock, and the PLL clock is used as system clock), a detected failure causes a switch of the system clock and the disabling of the HSE oscillator.
Page 185: Watchdog Clock
RM0367 Reset and clock control (RCC) 7.2.13 Watchdog clock If the Independent watchdog (IWDG) is started by either hardware option or software access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator temporization, the clock is provided to the IWDG. If the IWDG was enabled by software, the LSI clock is disabled after system reset.
Page 186: Clock-Independent System Clock Sources For Tim2/Tim21/Tim22
Reset and clock control (RCC) RM0367 The primary purpose of connecting the LSE to the channel 1 input capture is to be able to accurately measure the HSI16 and MSI system clocks (for this, either the HSI16 or MSI should be used as the system clock source). The number of HSI16 (MSI, respectively) clock counts between consecutive edges of the LSE signal provides a measure of the internal clock period.
Page 187: Rcc Registers
RM0367 Reset and clock control (RCC) RCC registers Refer to Section 1.2 for a list of abbreviations used in register descriptions. 7.3.1 Clock control register (RCC_CR) Address offset: 0x00 System Reset value: 0b0000 0000 00XX 0X00 0000 0011 0000 0000 where X is undefined Power-on reset value: 0x0000 0300 Access: no wait state, word, half-word and byte access CSSHS...
Page 188 Reset and clock control (RCC) RM0367 Bit 18 HSEBYP: HSE clock bypass bit This bit is set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled.
Page 189 RM0367 Reset and clock control (RCC) Bit 2 HSI16RDYF: Internal high-speed clock ready flag This bit is set by hardware to indicate that the HSI 16 MHz oscillator is stable. After the HSI16ON bit is cleared, HSI16RDY goes low after 6 HSI16 clock cycles. 0: HSI 16 MHz oscillator not ready 1: HSI 16 MHz oscillator ready Bit 1 HSI16KERON: High-speed internal clock enable bit for some IP kernels...
Page 190: Internal Clock Sources Calibration Register (Rcc_Icscr)
Reset and clock control (RCC) RM0367 7.3.2 Internal clock sources calibration register (RCC_ICSCR) Address offset: 0x04 Reset value: 0x00XX B0XX where X is undefined. Access: no wait state, word, half-word and byte access MSITRIM[7:0] MSICAL[7:0] MSIRANGE[2:0] HSI16TRIM[4:0] HSI16CAL[7:0] Bits 31:24 MSITRIM[7:0]: MSI clock trimming These bits are set by software to adjust MSI calibration.
Page 191: Clock Recovery Rc Register (Rcc_Crrcr)
RM0367 Reset and clock control (RCC) 7.3.3 Clock recovery RC register (RCC_CRRCR) Address: 0x08 Reset value: 0x0000 XX00 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 192: Clock Configuration Register (Rcc_Cfgr)
Reset and clock control (RCC) RM0367 7.3.4 Clock configuration register (RCC_CFGR) Address offset: 0x0C Reset value: 0x0000 0000 ≤ ≤ Access: 0 wait state 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during clock source switch. Res.
Page 193 RM0367 Reset and clock control (RCC) Bits 21:18 PLLMUL[3:0]: PLL multiplication factor These bits are written by software to define the PLL multiplication factor to generate the PLL VCO clock. These bits can be written only when the PLL is disabled. 0000: PLLVCO = PLL clock entry x 3 0001: PLLVCO = PLL clock entry x 4 0010: PLLVCO = PLL clock entry x 6...
Page 194: Clock Interrupt Enable Register (Rcc_Cier)
Reset and clock control (RCC) RM0367 Bits 7:4 HPRE[3:0]: AHB prescaler These bits are set and cleared by software to control the division factor of the AHB clock. Caution: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details please refer to the Dynamic voltage scaling management section in the PWR chapter.) After a write operation to these bits and before...
Page 195 RM0367 Reset and clock control (RCC) Bits 31:8 Reserved, must be kept at reset value. Bit 7 CSSLSE: LSE CSS interrupt flag This bit is set and reset by software to enable/disable the interrupt caused by the Clock Security System on external 32 kHz oscillator. 0: LSE CSS interrupt disabled 1: LSE CSS interrupt enabled Bit 6 HSI48RDYIE: HSI48 ready interrupt flag...
Page 196: Clock Interrupt Flag Register (Rcc_Cifr)
Reset and clock control (RCC) RM0367 7.3.6 RCC_CIFR) Clock interrupt flag register ( Address: 0x14 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 197: Clock Interrupt Clear Register (Rcc_Cicr)
RM0367 Reset and clock control (RCC) Bit 2 HSI16RDYF: HSI16 ready interrupt flag This bit is reset by software by writing the HSI16RDYC bit. It is set by hardware when the HSE clock becomes stable and the HSI16RDYIE is set. 0: No clock ready interrupt caused by HSI16 clock failure 1: Clock ready interrupt caused by HSI16 clock failure Bit 1 LSERDYF: LSE ready interrupt flag...
Page 198: Gpio Reset Register (Rcc_Ioprstr)
Reset and clock control (RCC) RM0367 Bit 5 MSIRDYC: MSI ready Interrupt clear This bit is set by software to clear the MSIRDYF flag. It is reset by hardware. 0: No effect 1: MSIRDYF flag cleared Bit 4 PLLRDYC: PLL ready Interrupt clear This bit is set by software to clear the PLLRDYF flag.
Page 199: Ahb Peripheral Reset Register (Rcc_Ahbrstr)
RM0367 Reset and clock control (RCC) Bits 6:5 Reserved, must be kept at reset value. Bit 4 IOPERST: I/O port E reset This bit is set and cleared by software. 0: no effect 1: resets I/O port E Bit 3 IOPDRST: I/O port D reset This bit is set and cleared by software.
Page 200: Apb2 Peripheral Reset Register (Rcc_Apb2Rstr)
Reset and clock control (RCC) RM0367 Bits 19:17 Reserved, must be kept at reset value. Bit 16 TSCRST: Touch Sensing reset This bit is set and reset by software. 0: no effect 1: resets Touch sensing module Bits 15: 13 Reserved, must be kept at reset value. Bit 12 CRCRST: Test integration module reset This bit is set and reset by software.
Page 201: Apb1 Peripheral Reset Register (Rcc_Apb1Rstr)
RM0367 Reset and clock control (RCC) Bit 14 USART1RST: USART1 reset This bit is set and cleared by software. 0: No effect 1: Reset USART1 Bit 13 Reserved, must be kept at reset value. Bit 12 SPI1RST: SPI 1 reset This bit is set and cleared by software.
Page 202 Reset and clock control (RCC) RM0367 Bit 31 LPTIM1RST: Low-power timer reset This bit is set and cleared by software. 0: No effect 1: Resets low-power timer Bit 30 I2C3RST: I2C3 reset This bit is set and cleared by software. 0: No effect 1: Resets I2C3 Bit 29 DACRST: DAC interface reset...
Page 203 RM0367 Reset and clock control (RCC) Bit 17 USART2RST: USART2 reset This bit is set and cleared by software. 0: No effect 1: Resets USART2 Bits 16:15 Reserved, must be kept at reset value. Bit 14 SPI2RST: SPI2 reset This bit is set and cleared by software. 0: No effect 1: Resets SPI2 Bits 13:12 Reserved, must be kept at reset value.
Page 204: Gpio Clock Enable Register (Rcc_Iopenr)
Reset and clock control (RCC) RM0367 7.3.12 GPIO clock enable register (RCC_IOPENR) Address: 0x2C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 205: Ahb Peripheral Clock Enable Register (Rcc_Ahbenr)
RM0367 Reset and clock control (RCC) 7.3.13 AHB peripheral clock enable register (RCC_AHBENR) Address offset: 0x30 Reset value: 0x0000 0100 Access: no wait state, word, half-word and byte access When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0.
Page 206 Reset and clock control (RCC) RM0367 Bit 8 MIFEN: NVM interface clock enable bit This bit is set and reset by software. This reset can be activated only when the NVM is in power-down mode. 0: NVM interface clock disabled 1: NVM interface clock enabled Bits 7:1 Reserved, must be kept at reset value.
Page 207: Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr)
RM0367 Reset and clock control (RCC) 7.3.14 APB2 peripheral clock enable register (RCC_APB2ENR) Address: 0x34 Reset value: 0x0000 0000 Access: word, half-word and byte access No wait states, except if the access occurs while an access to a peripheral in the APB2 domain is on going.
Page 208 Reset and clock control (RCC) RM0367 Bit 6 Reserved, must be kept at reset value. Bit 5 TIM22EN: TIM22 timer clock enable bit This bit is set and cleared by software. 0:TIM22 clock disabled 1: TIM22 clock enabled Bits 4:3 Reserved, must be kept at reset value. Bit 2 TIM21EN: TIM21 timer clock enable bit This bit is set and cleared by software.
Page 209: Apb1 Peripheral Clock Enable Register (Rcc_Apb1Enr)
RM0367 Reset and clock control (RCC) 7.3.15 APB1 peripheral clock enable register (RCC_APB1ENR) Address: 0x38 Reset value: 0x0000 0000 Access: word, half-word and byte access No wait state, except if the access occurs while an access to a peripheral on APB1 domain is on going.
Page 210 Reset and clock control (RCC) RM0367 Bit 22 I2C2EN: I2C2 clock enable bit This bit is set and cleared by software. 0: I2C2 clock disabled 1: I2C2 clock enabled Bit 21 I2C1EN: I2C1 clock enable bit This bit is set and cleared by software. 0: I2C1 clock disabled 1: I2C1 clock enabled Bit 20 USART5EN: USART5 clock enable bit...
Page 211 RM0367 Reset and clock control (RCC) Bit 4 TIM6EN: Timer 6 clock enable bit Set and cleared by software. 0: Timer 6 clock disabled 1: Timer 6 clock enabled Bits 3:2 Reserved, must be kept at reset value. Bit 1 TIM3EN: Timer3 clock enable bit Set and cleared by software.
Page 212: Gpio Clock Enable In Sleep Mode Register (Rcc_Iopsmenr)
Reset and clock control (RCC) RM0367 7.3.16 GPIO clock enable in Sleep mode register (RCC_IOPSMENR) Address: 0x3C Reset value: the bits corresponding to the available GPIO ports are set Access: no wait state, word, half-word and byte access Res. Res. Res.
Page 213: Ahb Peripheral Clock Enable In Sleep Mode Register (Rcc_Ahbsmenr)
RM0367 Reset and clock control (RCC) 7.3.17 AHB peripheral clock enable in Sleep mode register (RCC_AHBSMENR) Address: 0x40 Reset value: the bits corresponding to the available peripherals are set Access: no wait state, word, half-word and byte access CRYP RNGS TSCSM Res.
Page 214: Apb2 Peripheral Clock Enable In Sleep Mode Register (Rcc_Apb2Smenr)
Reset and clock control (RCC) RM0367 Bit 8 MIFSMEN: NVM interface clock enable during Sleep mode bit This bit is set and reset by software. 0: NVM interface clock disabled in Sleep mode 1: NVM interface clock enabled in Sleep mode Bits 7:1 Reserved, must be kept at reset value.
Page 215: Apb1 Peripheral Clock Enable In Sleep Mode Register (Rcc_Apb1Smenr)
RM0367 Reset and clock control (RCC) Bits 8:6 Reserved, must be kept at reset value. Bit 5 TIM22SMEN: TIM22 timer clock enable during Sleep mode bit This bit is set and cleared by software. 0:TIM22 clock disabled in Sleep mode 1: TIM22 clock enabled in Sleep mode (if enabled by TIM22EN) Bits 4:3 Reserved, must be kept at reset value.
Page 216 Reset and clock control (RCC) RM0367 Bit 28 PWRSMEN: Power interface clock enable during Sleep mode bit This bit is set and cleared by software. 0: Power interface clock disabled in Sleep mode 1: Power interface clock enabled in Sleep mode (if enabled by PWREN) Bit 27 CRSSMEN: Clock recovery system clock enable during Sleep mode bit This bit is set and cleared by software.
Page 217: Clock Configuration Register (Rcc_Ccipr)
RM0367 Reset and clock control (RCC) Bit 11 WWDGSMEN: Window watchdog clock enable during Sleep mode bit This bit is set and cleared by software. 0: Window watchdog clock disabled in Sleep mode 1: Window watchdog clock enabled in Sleep mode (if enabled by WWDGEN) Bit 10 Reserved, must be kept at reset value.
Page 218 Reset and clock control (RCC) RM0367 Bits 31:27 Reserved, must be kept at reset value. Bit26 HSI48SEL: 48 MHz HSI48 clock source selection bit This bit is set and cleared by software to select the HSI48 clock source for USB and RNG. 0: PLL USB clock selected as HSI48 clock 1: RC48 clock selected as HSI48 clock Bits 25:20 Reserved, must be kept at reset value.
Page 219: Control/Status Register (Rcc_Csr)
RM0367 Reset and clock control (RCC) 7.3.21 Control/status register (RCC_CSR) Address: 0x50 Power-on reset value: 0x0C00 0000 ≤ ≤ Access: 0 wait state 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. Note: The LSEON, LSEBYP, RTCSEL,LSEDRV and RTCEN bits in the RCC control and status register (RCC_CSR) are in the RTC domain.
Page 220 Reset and clock control (RCC) RM0367 Bit 26 PINRSTF: PIN reset flag This bit is set by hardware when a reset from the NRST pin occurs. It is cleared by writing to the RMVF bit, or by a POR. 0: No reset from NRST pin occurred 1: Reset from NRST pin occurred Bit 25 OBLRSTF Options bytes loading reset flag This bit is set by hardware when an OBL reset occurs.
Page 221 RM0367 Reset and clock control (RCC) Bit 14 CSSLSED: CSS on LSE failure detection flag This bit is set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator (LSE). It is cleared by a power-on reset or by an RTC software reset (RTCRST bit).
Page 222 Reset and clock control (RCC) RM0367 Bits 7:3 Reserved, must be kept at reset value. Bit 1 LSIRDY: Internal low-speed oscillator ready bit This bit is set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles.
Page 223: Rcc Register Map
RM0367 Reset and clock control (RCC) 7.3.22 RCC register map The following table gives the RCC register map and the reset values. Table 42. RCC register map and reset values Off- Register RCC_CR 0x00 [1:0] Reset value X X 0 X 0 0 0 0 0 0 0 0 MSIRAN HSI16TRIM[4:0...
Page 224 Reset and clock control (RCC) RM0367 Table 42. RCC register map and reset values (continued) Off- Register RCC_APB2RSTR 0x24 Reset value RCC_APB1RSTR 0x28 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 RCC_IOPENR 0x2C Reset value 0 0 0 0 0 RCC_AHBENR 0x30...
Page 225 RM0367 Reset and clock control (RCC) Table 42. RCC register map and reset values (continued) Off- Register RCC_APB1SMENR 0x48 Reset value 1 1 1 1 1 1 1 1 1 1 1 1 RCC_CCIPR 0x4C Reset value 0 0 0 0 0 0 0 0 RCC_CSR 0x50...
Page 226: Clock Recovery System (Crs)
Clock recovery system (CRS) RM0367 Clock recovery system (CRS) Introduction The clock recovery system (CRS) is an advanced digital controller acting on the internal fine-granularity trimmable RC oscillator HSI48. The CRS provides powerful means for oscillator output frequency evaluation, based on comparison with a selectable synchronization signal.
Page 227: Crs Functional Description
RM0367 Clock recovery system (CRS) CRS functional description 8.4.1 CRS block diagram Figure 19. CRS block diagram CRS_SYNC GPIO SYNCSRC SWSYNC OSC32_IN SYNC divider (/1,/2,/4,…,/128) OSC32_OUT SYNC USB_DP FELIM USB_DM TRIM FEDIR FECAP RC 48 MHz 16-bit counter RELOAD HSI48 To USB To RNG MSv34708V1...
Page 228: Frequency Error Measurement
Clock recovery system (CRS) RM0367 8.4.3 Frequency error measurement The frequency error counter is a 16-bit down/up counter which is reloaded with the RELOAD value on each SYNC event. It starts counting down till it reaches the zero value, where the ESYNC (expected synchronization) event is generated.
Page 229: Frequency Error Evaluation And Automatic Trimming
RM0367 Clock recovery system (CRS) 8.4.4 Frequency error evaluation and automatic trimming The measured frequency error is evaluated by comparing its value with a set of limits: – TOLERANCE LIMIT, given directly in the FELIM field of the CRS_CFGR register –...
Page 230: Felim Value
Clock recovery system (CRS) RM0367 FELIM value The selection of the FELIM value is closely coupled with the HSI48 oscillator characteristics and its typical trimming step size. The optimal value corresponds to half of the trimming step size, expressed as a number of HSI48 oscillator clock ticks. The following formula can be used: FELIM = (f ) * STEP[%] / 100% / 2...
Page 231: Crs Registers
RM0367 Clock recovery system (CRS) CRS registers Refer to Section 1.2 on page 52 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed only by words (32-bit). 8.7.1 CRS control register (CRS_CR) Address offset: 0x00 Reset value: 0x0000 2000 Res.
Page 232: Crs Configuration Register (Crs_Cfgr)
Clock recovery system (CRS) RM0367 Bit 2 ERRIE: Synchronization or trimming error interrupt enable 0: Synchronization or trimming error (ERRF) interrupt disabled 1: Synchronization or trimming error (ERRF) interrupt enabled Bit 1 SYNCWARNIE: SYNC warning interrupt enable 0: SYNC warning (SYNCWARNF) interrupt disabled 1: SYNC warning (SYNCWARNF) interrupt enabled Bit 0 SYNCOKIE: SYNC event OK interrupt enable 0: SYNC event OK (SYNCOKF) interrupt disabled...
Page 233: Crs Interrupt And Status Register (Crs_Isr)
RM0367 Clock recovery system (CRS) Bits 26:24 SYNCDIV[2:0]: SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal. 000: SYNC not divided (default) 001: SYNC divided by 2 010: SYNC divided by 4 011: SYNC divided by 8 100: SYNC divided by 16 101: SYNC divided by 32...
Page 234 Clock recovery system (CRS) RM0367 Bit 9 SYNCMISS: SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action has to be taken.
Page 235: Crs Interrupt Flag Clear Register (Crs_Icr)
RM0367 Clock recovery system (CRS) 8.7.4 CRS interrupt flag clear register (CRS_ICR) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYNC SYNC Res. Res. Res. Res.
Page 236: Crs Register Map
Clock recovery system (CRS) RM0367 8.7.5 CRS register map Table 46. CRS register map and reset values Offset Register TRIM[5:0] CRS_CR 0x00 Reset value SYNC SYNC CRS_CFGR FELIM[7:0] RELOAD[15:0] 0x04 [1:0] [2:0] Reset value CRS_ISR FECAP[15:0] 0x08 Reset value CRS_ICR 0x0C Reset value Refer to...
Page 237: General-Purpose I/Os (Gpio)
RM0367 General-purpose I/Os (GPIO) General-purpose I/Os (GPIO) Introduction Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). In addition all GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection registers (GPIOx_AFRH and GPIOx_AFRL).
Page 238: Figure 21. Basic Structure Of An I/O Port Bit
General-purpose I/Os (GPIO) RM0367 Figure 21 Figure 22 show the basic structures of a standard and a 5-Volt tolerant I/O port bit, respectively. Table 47 gives the possible port bit configurations. Figure 21. Basic structure of an I/O port bit Analog To on-chip peripheral...
Page 239: General-Purpose I/O (Gpio)
RM0367 General-purpose I/Os (GPIO) Table 47. Port bit configuration table MODE(i) OSPEED(i) PUPD(i) OTYPER(i) I/O configuration [1:0] [1:0] [1:0] GP output GP output PP + PU GP output PP + PD Reserved SPEED [1:0] GP output GP output OD + PU GP output OD + PD Reserved (GP output OD)
Page 240: I/O Pin Alternate Function Multiplexer And Mapping
General-purpose I/Os (GPIO) RM0367 When the pin is configured as output, the value written to the output data register (GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull mode or open-drain mode (only the low level is driven, high level is HI-Z). The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB clock cycle.
Page 241: I/O Port Control Registers
RM0367 General-purpose I/Os (GPIO) 9.3.3 I/O port control registers Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The GPIOx_MODER register is used to select the I/O mode (input, output, AF, analog). The GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (push- pull or open-drain) and speed.
Page 242: I/O Alternate Function Input/Output
General-purpose I/Os (GPIO) RM0367 The LOCK sequence (refer to Section 9.4.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A to E and H)) can only be performed using a word (32-bit long) access to the GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same time as the [15:0] bits.
Page 243: Output Configuration
RM0367 General-purpose I/Os (GPIO) Figure 23. Input floating/pull up/pull down configurations Read V DDIOx V DDIOx on/off TTL Schmitt protection trigger diode pull Write input driver I/O pin on/off output driver protection pull diode down V SS V SS Read/write MS31477V1 9.3.10 Output configuration...
Page 244: Alternate Function Configuration
General-purpose I/Os (GPIO) RM0367 Figure 24 shows the output configuration of the I/O port bit. Figure 24. Output configuration Read TTL Schmitt DDIOx DDIOx trigger on/off protection Write Input driver diode pull I/O pin Output driver DDIOx on/off P-MOS protection pull Output down...
Page 245: Analog Configuration
RM0367 General-purpose I/Os (GPIO) Figure 25 shows the alternate function configuration of the I/O port bit. Figure 25. Alternate function configuration To on-chip Alternate function input peripheral Read VDDIOx VDDIOx TTL Schmitt on/off trigger protection Pull diode Input driver Write I/O pin on/off Output driver...
Page 246: Using The Hse Or Lse Oscillator Pins As Gpios
General-purpose I/Os (GPIO) RM0367 9.3.13 Using the HSE or LSE oscillator pins as GPIOs When the HSE or LSE oscillator is switched OFF (default state after reset), the related oscillator pins can be used as normal GPIOs. When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the RCC_CSR register) the oscillator takes control of its associated pins and the GPIO configuration of these pins has no effect.
Page 247: Gpio Port Output Type Register (Gpiox_Otyper)
RM0367 General-purpose I/Os (GPIO) 9.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A to E and H) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 248: Gpio Port Pull-Up/Pull-Down Register (Gpiox_Pupdr)
General-purpose I/Os (GPIO) RM0367 9.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to E and H) Address offset: 0x0C Reset value: 0x2400 0000 (for port A) Reset value: 0x0000 0000 (for the other ports) PUPD15[1:0] PUPD14[1:0] PUPD13[1:0] PUPD12[1:0] PUPD11[1:0] PUPD10[1:0] PUPD9[1:0] PUPD8[1:0]...
Page 249: Gpio Port Output Data Register (Gpiox_Odr)
RM0367 General-purpose I/Os (GPIO) 9.4.6 GPIO port output data register (GPIOx_ODR) (x = A to E and H) Address offset: 0x14 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 250 General-purpose I/Os (GPIO) RM0367 LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. Note: A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.
Page 251: Gpio Alternate Function Low Register (Gpiox_Afrl)
RM0367 General-purpose I/Os (GPIO) 9.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A to E and H) Address offset: 0x20 Reset value: 0x0000 0000 AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0] AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0] Bits 31:0 AFSEL[7:0][3:0]: Alternate function selection for port x I/O pin y (y = 7 to 0) These bits are written by software to configure alternate function I/Os.
Page 252: Gpio Port Bit Reset Register (Gpiox_Brr) (X = A To E And H)
General-purpose I/Os (GPIO) RM0367 Bits 31:0 AFSEL[15:8][3:0]: Alternate function selection for port x I/O pin y (y = 15 to 8) These bits are written by software to configure alternate function I/Os. 0000: AF0 0001: AF1 0010: AF2 0011: AF3 0100: AF4 0101: AF5 0110: AF6...
Page 253: Gpio Register Map
RM0367 General-purpose I/Os (GPIO) 9.4.12 GPIO register map The following table gives the GPIO register map and reset values. Table 48. GPIO register map and reset values Offset Register name GPIOA_MODER 0x00 Reset value 1 1 1 1 1 1 1 1 1 1 1 1 GPIOx_MODER (where x = B..E, H) 0x00...
Page 254 General-purpose I/Os (GPIO) RM0367 Table 48. GPIO register map and reset values (continued) Offset Register name GPIOx_AFRL AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0] AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0] (where x = A..E,H) 0x20 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_AFRH AFSEL15[3:0 AFSEL14[3:0...
Page 255: System Configuration Controller (Syscfg)
EVENTOUT, during SEV instruction execution. In STM32L0x3 devices, an event input can be generated by an external interrupt line or by an RTC alarm interrupt. It is also possible to select which output pin is connected to the ®...
Page 256: Syscfg Registers
System configuration controller (SYSCFG) RM0367 10.2 SYSCFG registers The peripheral registers have to be accessed by words (32-bit). 10.2.1 SYSCFG memory remap register (SYSCFG_CFGR1) This register is used for specific configurations related to memory remap: Note: This register is not reset through the SYSCFGRST bit in the RCC_APB2RSTR register. Address offset: 0x00 Reset value: 0x000x 000x (X is the memory mode selected by the boot configuration).
Page 257 RM0367 System configuration controller (SYSCFG) Bit 3 UFB: User bank swapping This bit is available only on category 5 devices and reserved on other categories. It is set and cleared by software. It controls the Bank 1/2 mapping (see Table 8: NVM organization for UFB = 0 (128 Kbyte category 5 devices) Table 10: NVM organization for UFB = 0 (64 Kbyte category 5...
Page 258: Syscfg Peripheral Mode Configuration Register (Syscfg_Cfgr2)
System configuration controller (SYSCFG) RM0367 10.2.2 SYSCFG peripheral mode configuration register (SYSCFG_CFGR2) Address offset: 0x04 Reset value: 0x0000 0001 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. I2C3_ I2C_PB9 I2C_PB8 I2C_PB7 I2C_PB6 Res.
Page 259: Reference Control And Status Register (Syscfg_Cfgr3)
RM0367 System configuration controller (SYSCFG) Bits 7:4 Reserved, must be kept at reset value Bits 5:1 LCD_CAPA[4:0]: Decoupling capacitance connection (refer to the datasheet for details on the device capability) These bits are set and cleared by software. They control the connection of the internal V rails supply voltage to a dedicated I/O (LCD_VLCD1, LCD_VLCD2, LCD_VLCD3) to perform an optional decoupling.
Page 260 System configuration controller (SYSCFG) RM0367 Bit 31 REF_LOCK: SYSCFG_CFGR3 lock bit This bit is set by software and cleared by a hardware system reset. It locks the whole content of the reference control/Status register, SYSCFG_CFGR3[31:0]. 0: SYSCFG_CFGR3[31:0] bits are read/write 1: SYSCFG_CFGR3[31:0] bits are read-only Bit 30 VREFINT_RDYF: VREFINT ready flag This bit is read-only.
Page 261: Syscfg External Interrupt Configuration Register 1
RM0367 System configuration controller (SYSCFG) Bits 5:4 SEL_VREF_OUT: VREFINT_ADC connection bit These bits are set and cleared by software (only if REF_LOCK not set). These bits select which pad is connected to VREFINT_ADC when ENBUF_VREFINT_ADC is set. 00: no pad connected 01: PB0 connected 10: PB1 connected 11: PB0 and PB1 connected...
Page 262: Syscfg External Interrupt Configuration Register 2
System configuration controller (SYSCFG) RM0367 10.2.5 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) Address offset: 0x0C Reset value: 0x0000 Reserved EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0] Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 4 to 7) These bits are written by software to select the source input for the EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin...
Page 263: Syscfg External Interrupt Configuration Register 4
RM0367 System configuration controller (SYSCFG) 10.2.7 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) Address offset: 0x14 Reset value: 0x0000 Reserved EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 12 to 15) These bits are written by software to select the source input for the EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin...
Page 264 System configuration controller (SYSCFG) RM0367 Table 49. SYSCFG register map and reset values (continued) Offset Register SYSCFG_ EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0] EXTICR3 0x10 Reset value SYSCFG_ EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] EXTICR4 0x14 Reset value 0x18 COMP1_CTRL Refer to Section 16: Comparator (COMP) 0x1C COMP2_CTRL SYSCFG_CFGR3...
Page 265: Direct Memory Access Controller (Dma)
RM0367 Direct memory access controller (DMA) Direct memory access controller (DMA) 11.1 Introduction The direct memory access (DMA) controller is a bus master and system peripheral. The DMA is used to perform programmable data transfers between memory-mapped peripherals and/or memories, upon the control of an off-loaded CPU. The DMA controller features a single AHB master architecture.
Page 266: Dma Implementation
Direct memory access controller (DMA) RM0367 11.3 DMA implementation 11.3.1 DMA is implemented with the hardware configuration parameters shown in the table below. Table 50. DMA implementation Feature Number of channels 11.3.2 DMA request mapping DMA controller The hardware requests from the peripherals (TIM2/6, ADC, DAC, SPI1/2, I2C1/2, AES (available only on category 3 and 5 devices, with AES), USART1/2 and LPUART1) are mapped to the DMA channels through the DMA_CSELR channel selection registers (see Figure...
Page 267: Table 51. Dma Requests For Each Channel
RM0367 Direct memory access controller (DMA) Figure 27. DMA request mapping Fixed hardware priority Peripheral request signals High priority ADC, TIM2_CH3,AES_IN SW trigger 1 (MEM2MEM bit) ADC,SPI1_RX,USART1_TX, LPUART1_TX,I2C1_TX,I2C3_TX, TIM2_UP,TIM6_UP/DAC chan. 1, AES_OUT,TIM3_CH3, USART4_RX, USART5_RX SW trigger 2 (MEM2MEM bit) SPI1_TX, USART1_RX,I2C3_RX LPUART1_RX, I2C1_RX, TIM2_CH2, TIM3_CH4,TIM3_UP, USART4_TX,USART5_TX,...
Page 268: Dma Functional Description
Direct memory access controller (DMA) RM0367 Table 51. DMA requests for each channel (continued) CxS[3:0] Peripheral Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 0111 I2C2 I2C2_TX I2C2_RX TIM2_ TIM2_CH2 1000 TIM2 TIM2_UP TIM2_CH2 TIM2_CH4 TIM2_CH1 TIM2_CH4 TIM6_UP/ TIM6_UP/...
Page 269: Dma Transfers
RM0367 Direct memory access controller (DMA) The DMA block diagram is shown in the figure below. Figure 28. DMA block diagram FLITF Flash System Cortex- SRAM Reset & Ch.1 Clock control Ch.2 (RCC) up to Bridge Ch.7 Arbiter AHB Slave DMA request SPI1/SPI2 USART1/2/4/5...
Page 270: Dma Arbitration
Direct memory access controller (DMA) RM0367 After an event, the following steps of a single DMA transfer occur: The peripheral sends a single DMA request signal to the DMA controller. The DMA controller serves the request, depending on the priority of the channel associated to this peripheral request.
Page 271: Dma Channels
RM0367 Direct memory access controller (DMA) The priorities are managed in two stages: • software: priority of each channel is configured in the DMA_CCRx register, to one of the four different levels: – very high – high – medium – •...
Page 272: Channel Configuration Procedure
Direct memory access controller (DMA) RM0367 Channel configuration procedure The following sequence is needed to configure a DMA channel x: Set the peripheral register address in the DMA_CPARx register. The data is moved from/to this address to/from the memory after the peripheral event, or after the channel is enabled in memory-to-memory mode.
Page 273: Circular Mode (In Memory-To-Peripheral/Peripheral-To-Memory Transfers)
RM0367 Direct memory access controller (DMA) register content may not correctly reflect the remaining data transfers versus the aborted source and destination buffer/register. • Abort and restart a channel This corresponds to the software sequence: disable an active channel, then reconfigure the channel and enable it again.
Page 274: Peripheral-To-Peripheral Mode
Direct memory access controller (DMA) RM0367 Peripheral-to-peripheral mode Any DMA channel can operate in peripheral-to-peripheral mode: • when the hardware request from a peripheral is selected to trigger the DMA channel This peripheral is the DMA initiator and paces the data transfer from/to this peripheral to/from a register belonging to another memory-mapped peripheral (this one being not configured in DMA mode).
Page 275: Addressing Ahb Peripherals Not Supporting Byte/Half-Word Write Transfers
RM0367 Direct memory access controller (DMA) Table 52. Programmable data width and endian behavior (when PINC = MINC = 1) Source Destinat Destination port ion port Source content: Number width content: width address / data of data (PSIZE address / data (MSIZE items to DMA transfers...
Page 276: Dma Error Management
Direct memory access controller (DMA) RM0367 Assuming the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take into account the HSIZE data, any AHB byte or half-word transfer is changed into a 32-bit APB transfer as described below: •...
Page 277: Dma Interrupt Status Register (Dma_Isr)
RM0367 Direct memory access controller (DMA) 11.6.1 DMA interrupt status register (DMA_ISR) Address offset: 0x00 Reset value: 0x0000 0000 Every status bit is cleared by hardware when the software sets the corresponding clear bit or the corresponding global clear bit CGIFx, in the DMA_IFCR register. Res.
Page 278 Direct memory access controller (DMA) RM0367 Bit 17 TCIF5: transfer complete (TC) flag for channel 5 0: no TC event 1: a TC event occurred Bit 16 GIF5: global interrupt flag for channel 5 0: no TE, HT or TC event 1: a TE, HT or TC event occurred Bit 15 TEIF4: transfer error (TE) flag for channel 4 0: no TE event...
Page 279: Dma Interrupt Flag Clear Register (Dma
RM0367 Direct memory access controller (DMA) Bit 2 HTIF1: half transfer (HT) flag for channel 1 0: no HT event 1: a HT event occurred Bit 1 TCIF1: transfer complete (TC) flag for channel 1 0: no TC event 1: a TC event occurred Bit 0 GIF1: global interrupt flag for channel 1 0: no TE, HT or TC event 1: a TE, HT or TC event occurred...
Page 280: Dma Channel X Configuration Register (Dma_Ccrx)
Direct memory access controller (DMA) RM0367 Bit 17 CTCIF5: transfer complete flag clear for channel 5 Bit 16 CGIF5: global interrupt flag clear for channel 5 Bit 15 CTEIF4: transfer error flag clear for channel 4 Bit 14 CHTIF4: half transfer flag clear for channel 4 Bit 13 CTCIF4: transfer complete flag clear for channel 4 Bit 12 CGIF4: global interrupt flag clear for channel 4 Bit 11 CTEIF3: transfer error flag clear for channel 3...
Page 281 RM0367 Direct memory access controller (DMA) Bits 31:15 Reserved, must be kept at reset value. Bit 14 MEM2MEM: memory-to-memory mode 0: disabled 1: enabled Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).
Page 282 Direct memory access controller (DMA) RM0367 Bit 7 MINC: memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0.
Page 283: Dma Channel X Number Of Data To Transfer Register (Dma_Cndtrx)
RM0367 Direct memory access controller (DMA) Bit 2 HTIE: half transfer interrupt enable 0: disabled 1: enabled Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). Bit 1 TCIE: transfer complete interrupt enable 0: disabled 1: enabled...
Page 284: Dma Channel X Peripheral Address Register (Dma_Cparx)
Direct memory access controller (DMA) RM0367 11.6.5 DMA channel x peripheral address register (DMA_CPARx) Address offset: 0x10 + 0x14 * (x - 1), (x = 1 to 7) Reset value: 0x0000 0000 PA[31:16] PA[15:0] Bits 31:0 PA[31:0]: peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written.
Page 285 RM0367 Direct memory access controller (DMA) Bits 31:0 MA[31:0]: peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address.
Page 286: Dma Channel Selection Register (Dma_Cselr)
Direct memory access controller (DMA) RM0367 11.6.7 DMA channel selection register (DMA_CSELR) Address offset: 0xA8 Reset value: 0x0000 0000 This register is used to manage the mapping of DMA channels as detailed in Section 11.3.2: DMA request mapping. Res. Res. Res.
Page 287 RM0367 Direct memory access controller (DMA) Table 54. DMA register map and reset values (continued) Offset Register DMA_CNDTR1 NDTR[15:0] 0x00C Reset value DMA_CPAR1 PA[31:0] 0x010 Reset value DMA_CMAR1 MA[31:0] 0x014 Reset value 0x018 Reserved Reserved. DMA_CCR2 0x01C Reset value DMA_CNDTR2 NDTR[15:0] 0x020 Reset value...
Page 288 Direct memory access controller (DMA) RM0367 Table 54. DMA register map and reset values (continued) Offset Register DMA_CMAR5 MA[31:0] 0x064 Reset value 0x068 Reserved Reserved. DMA_CCR6 0x06C Reset value DMA_CNDTR6 NDTR[15:0] 0x070 Reset value DMA_CPAR6 PA[31:0] 0x074 Reset value DMA_CMAR6 MA[31:0] 0x078 Reset value...
Page 289: Nested Vectored Interrupt Controller (Nvic)
The SysTick calibration value is fixed to 4000, which gives a reference time base of 1 ms with the SysTick clock set to 4 MHz (max HCLK/8). 12.3 Interrupt and exception vectors Table 55 is the vector table for STM32L0x3 devices. (1)(2) Table 55. List of vectors Type of Position...
Page 290 Nested vectored interrupt controller (NVIC) RM0367 (1)(2) Table 55. List of vectors (continued) Type of Position Priority Acronym Description Address priority settable WWDG Window Watchdog interrupt 0x0000_0040 PVD through EXTI Line detection settable 0x0000_0044 interrupt RTC global interrupt through settable EXTI17/19/20 line and LSE CSS 0x0000_0048 interrupt through EXTI 19 line...
Page 291 ® 1. The grayed cells correspond to the Cortex -M0+ interrupts. 2. Refer to Table 1: STM32L0x3 memory density, to Table 2: Overview of features per category and to the device datasheets for the GPIO ports and peripherals available on your device. The memory area corresponding to unavailable GPIO ports or peripherals are reserved.
Page 292: Extended Interrupt And Event Controller (Exti)
Extended interrupt and event controller (EXTI) RM0367 Extended interrupt and event controller (EXTI) 13.1 Introduction The extended interrupts and events controller (EXTI) manages the external and internal asynchronous events/interrupts and generates the event request to the CPU/interrupt controller plus a wake-up request to the power controller. The EXTI allows the management of up to 30 event lines which can wake up the device from Stop mode.
Page 293: Exti Block Diagram
MSv32798V1 13.3.2 Wakeup event management The STM32L0x3 microcontrollers are able to handle external or internal events in order to wake up the core (WFE). The wakeup event can be generated by either: • enabling an interrupt in the peripheral control register but not in the NVIC, and enabling ®...
Page 294: Peripherals Asynchronous Interrupts
Extended interrupt and event controller (EXTI) RM0367 13.3.3 Peripherals asynchronous interrupts Some peripherals can generate events when the system is in Run mode or in Stop mode, thus allowing to wake up the system from Stop mode. To accomplish this, the peripheral generates both a synchronized (to the system clock, e.g. APB clock) and an asynchronous version of the event.
Page 295: Exti Interrupt/Event Line Mapping
RM0367 Extended interrupt and event controller (EXTI) 13.4 EXTI interrupt/event line mapping In the STM32L0x3, 30 interrupt/event lines are available.The GPIOs are connected to 16 configurable interrupt/event lines as shown in Figure Figure 30. Extended interrupt/event GPIO mapping EXTI0[3:0] bits in SYSCFG_EXTICR1 register...
Page 296: Table 56. Exti Lines Connections
Extended interrupt and event controller (EXTI) RM0367 The 30 lines are connected as shown in Table 56: EXTI lines connections: Table 56. EXTI lines connections EXTI line Line source Line type 0-15 GPIO configurable configurable RTC alarm configurable USB wakeup event direct RTC tamper or timestamp or configurable...
Page 297: Exti Registers
RM0367 Extended interrupt and event controller (EXTI) 13.5 EXTI registers Refer to Section 1.2 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 13.5.1 EXTI interrupt mask register (EXTI_IMR) Address offset: 0x00 Reset value: 0x3F84 0000 Res.
Page 298: Exti Rising Edge Trigger Selection Register (Exti_Rtsr)
Extended interrupt and event controller (EXTI) RM0367 Bits 31:30 Reserved, must be kept at reset value. Bits 29:28 EMx: Event mask on line x (x = 29 to 28) 0: Event request from Line x is masked 1: Event request from Line x is not masked Bit 27 Reserved, must be kept at reset value.
Page 299: Falling Edge Trigger Selection Register (Exti_Ftsr)
RM0367 Extended interrupt and event controller (EXTI) 13.5.4 Falling edge trigger selection register (EXTI_FTSR) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. FT22 FT21 FT20 FT19 Res. FT17 FT16 FT15 FT14 FT13 FT12 FT11 FT10...
Page 300: Exti Pending Register (Exti_Pr)
Extended interrupt and event controller (EXTI) RM0367 Bits 31:23 Reserved, must be kept at reset value. Bits 22:19 SWIx: Software interrupt on line x (x = 22 to 19) Writing a 1 to this bit when it is at 0 sets the corresponding pending bit in EXTI_PR. If the interrupt is enabled on this line in EXTI_IMR and EXTI_EMR, an interrupt request is generated.
Page 301: Exti Register Map
RM0367 Extended interrupt and event controller (EXTI) 13.5.7 EXTI register map The following table gives the EXTI register map and the reset values. Table 57. Extended interrupt/event controller register map and reset values Offset Register EXTI_IMR IM[26:19] IM[17:0] 0x00 Reset value 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI_EMR...
Page 302: Analog-To-Digital Converter (Adc)
Analog-to-digital converter (ADC) RM0367 Analog-to-digital converter (ADC) 14.1 Introduction The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19 multiplexed channels allowing it to measure signals from 16 external and 3 internal sources. A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode.
Page 303: Adc Main Features
RM0367 Analog-to-digital converter (ADC) 14.2 ADC main features • High performance – 12-bit, 10-bit, 8-bit or 6-bit configurable resolution – ADC conversion time: 0.87 µs for 12-bit resolution (1.14 MHz), 0.81 µs conversion time for 10-bit resolution, faster conversion times can be obtained by lowering resolution.
Page 304: Adc Functional Description
Analog-to-digital converter (ADC) RM0367 14.3 ADC functional description Figure 31 shows the ADC block diagram and Table 58 gives the ADC pin description. Figure 31. ADC block diagram ADC V REF+ 1.65 to 3.6 V Analog supply SCANDIR up/ 1.8 to 3.6 V AREADY down EOSMP...
Page 305: Adc Voltage Regulator (Advregen)
RM0367 Analog-to-digital converter (ADC) Table 59. ADC internal input/output signals Internal signal Signal type Description name Analog Input Connected either to internal channels or to ADC_INi channels external channels TRGx Input ADC conversion triggers Input Internal temperature sensor output voltage SENSE Input Internal voltage reference output voltage...
Page 306: Advreg Enable Sequence
Analog-to-digital converter (ADC) RM0367 regulator is in low-power mode (with the device operating in LPRun, LPSleep or Stop mode), the voltage reference is disabled and the ADC cannot be used anymore. The software must follow the procedure described below to manage the ADC in low-power mode: Make sure that the ADC is disabled (ADEN = 0).
Page 307: Figure 32. Adc Calibration
RM0367 Analog-to-digital converter (ADC) The calibration factor is maintained in the following low-power modes: LPRun, LPSleep and Stop. It is still possible to save and restore the calibration factor by software to save time when re-starting the ADC (as long as temperature and voltage are stable during the ADC power down).
Page 308: Calibration Factor Forcing Software Procedure
Analog-to-digital converter (ADC) RM0367 Calibration factor forcing Software procedure Ensure that ADEN= 1 and ADSTART = 0 (ADC started with no conversion ongoing) Write ADC_CALFACT with the saved calibration factor The calibration factor is used as soon as a new conversion is launched. Figure 33.
Page 309: Adc Clock (Ckmode, Presc[3:0], Lfmen)
RM0367 Analog-to-digital converter (ADC) Follow this procedure to disable the ADC: Check that ADSTART = 0 in the ADC_CR register to ensure that no conversion is ongoing. If required, stop any ongoing conversion by writing 1 to the ADSTP bit in the ADC_CR register and waiting until this bit is read at 0.
Page 310: Low Frequency
Analog-to-digital converter (ADC) RM0367 The input clock of the analog ADC can be selected between two different clock sources (see Figure 35: ADC clock scheme to see how the PCLK clock and the ADC asynchronous clock are enabled): The ADC clock can be a specific clock source, named “ADC asynchronous clock“ which is independent and asynchronous with the APB clock.
Page 311: Adc Connectivity
RM0367 Analog-to-digital converter (ADC) 14.3.6 ADC connectivity ADC inputs are connected to the external channels as well as internal sources as described Figure Figure 36. ADC connectivity STM32L0x3 Channel selection Fast channel ADC_IN0 ADC_IN1 ADC_IN2 ADC_IN3 Fast channel ADC_IN4 Fast channel...
Page 312: Configuring The Adc
Analog-to-digital converter (ADC) RM0367 14.3.7 Configuring the ADC Software must write to the ADCAL and ADEN bits in the ADC_CR register if the ADC is disabled (ADEN must be 0). Software must only write to the ADSTART and ADDIS bits in the ADC_CR register only if the ADC is enabled and there is no pending request to disable the ADC (ADEN = 1 and ADDIS = 0).
Page 313: Programmable Sampling Time (Smp)
RM0367 Analog-to-digital converter (ADC) 14.3.9 Programmable sampling time (SMP) Before starting a conversion, the ADC needs to establish a direct connection between the voltage source to be measured and the embedded sampling capacitor of the ADC. This sampling time must be enough for the input voltage source to charge the sample and hold capacitor to the input voltage level.
Page 314: Continuous Conversion Mode (Cont = 1)
Analog-to-digital converter (ADC) RM0367 14.3.11 Continuous conversion mode (CONT In continuous conversion mode, when a software or hardware trigger event occurs, the ADC performs a sequence of conversions, converting all the channels once and then automatically re-starts and continuously performs the same sequence of conversions. This mode is selected when CONT = 1 in the ADC_CFGR1 register.
Page 315: Timings
RM0367 Analog-to-digital converter (ADC) the need for software having to set the ADSTART bit again and ensures the next trigger event is not missed. 14.3.13 Timings The elapsed time between the start of a conversion and the end of conversion is the sum of the configured sampling time plus the successive approximation time depending on data resolution: = [ 1.5...
Page 316: Stopping An Ongoing Conversion (Adstp)
Analog-to-digital converter (ADC) RM0367 14.3.14 Stopping an ongoing conversion (ADSTP) The software can decide to stop any ongoing conversions by setting ADSTP = 1 in the ADC_CR register. This resets the ADC operation and the ADC is idle, ready for a new operation. When the ADSTP bit is set by software, any ongoing conversion is aborted and the result is discarded (ADC_DR register is not updated with the current conversion).
Page 317: Discontinuous Mode (Discen)
RM0367 Analog-to-digital converter (ADC) Refer to Table 60: External triggers Section 14.3.1: ADC pins and internal signals for the list of all the external triggers that can be used for regular conversion. The software source trigger events can be generated by setting the ADSTART bit in the ADC_CR register.
Page 318: End Of Conversion, End Of Sampling Phase (Eoc, Eosmp Flags)
Analog-to-digital converter (ADC) RM0367 Table 63. t timings depending on resolution CONV SMPL (min) RES[1:0] (ns) at (ns) at CONV (ADC clock cycles) (ADC clock (ADC clock bits = 16 MHz = 16 MHz cycles) cycles) (with min. t SMPL) 12.5 781 ns 875 ns...
Page 319: Example Timing Diagrams
RM0367 Analog-to-digital converter (ADC) 14.4.5 Example timing diagrams (single/continuous modes hardware/software triggers) Figure 40. Single conversions of a sequence, software trigger ADSTART SCANDIR ADC state CH17 CH17 CH10 CH10 ADC_DR by S/W by H/W MSv30338V3 1. EXTEN = 00, CONT = 0 2.
Page 320: Figure 42. Single Conversions Of A Sequence, Hardware Trigger
Analog-to-digital converter (ADC) RM0367 Figure 42. Single conversions of a sequence, hardware trigger ADSTART TRGx ADC state ADC_DR by S/W by H/W triggered ignored MSv30340V2 1. EXTSEL = TRGx (over-frequency), EXTEN = 01 (rising edge), CONT = 0 2. CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 0 For code example, refer to A.8.7: Single conversion sequence code example - Hardware trigger.
Page 321: Data Management
RM0367 Analog-to-digital converter (ADC) 14.5 Data management 14.5.1 Data register and data alignment (ADC_DR, ALIGN) At the end of each conversion (when an EOC event occurs), the result of the converted data is stored in the ADC_DR data register which is 16-bit wide. The format of the ADC_DR depends on the configured data alignment and resolution.
Page 322: Managing A Sequence Of Data Converted Without Using The Dma
Analog-to-digital converter (ADC) RM0367 Figure 45. Example of overrun (OVR) ADSTART ADSTP TRGx ADC state CH0 STOP ADC_DR read OVERRUN access ADC_DR (OVRMOD=0) ADC_DR (OVRMOD=1) by S/W by H/W triggered MSv30343V3 14.5.3 Managing a sequence of data converted without using the DMA If the conversions are slow enough, the conversion sequence can be handled by software.
Page 323: Dma One Shot Mode (Dmacfg = 0)
RM0367 Analog-to-digital converter (ADC) converted data from the ADC_DR register to the destination location selected by the software. Note: The DMAEN bit in the ADC_CFGR1 register must be set after the ADC calibration phase. Despite this, if an overrun occurs (OVR = 1) because the DMA could not serve the DMA transfer request in time, the ADC stops generating DMA requests and the data corresponding to the new conversion is not transferred by the DMA.
Page 324: Low-Power Features
Analog-to-digital converter (ADC) RM0367 14.6 Low-power features 14.6.1 Wait mode conversion Wait mode conversion can be used to simplify the software as well as optimizing the performance of applications clocked at low frequency where there might be a risk of ADC overrun occurring.
Page 325: Auto-Off Mode (Autoff)
RM0367 Analog-to-digital converter (ADC) 14.6.2 Auto-off mode (AUTOFF) The ADC has an automatic power management feature which is called auto-off mode, and is enabled by setting AUTOFF = 1 in the ADC_CFGR1 register. When AUTOFF = 1, the ADC is always powered off when not converting and automatically wakes-up when a conversion is started (by software or hardware trigger).
Page 326: Analog Window Watchdog
Analog-to-digital converter (ADC) RM0367 Figure 48. Behavior with WAIT = 1, AUTOFF = 1 TRGx ADC_DR Read access Startup Startup Startup Startup ADC state ADC_DR by S/W by H/W triggered MSv30346V2 1. EXTSEL = TRGx, EXTEN = 01 (rising edge), CONT = x, ADSTART = 1, CHSEL = 0xF, SCANDIR = 0, WAIT = 1, AUTOFF = 1 For code example, refer to A.8.13: Auto off and wait mode sequence code...
Page 327: Adc_Awd1_Out Output Signal Generation
RM0367 Analog-to-digital converter (ADC) Table 64. Analog watchdog comparison Analog Watchdog comparison between: Resolution bits Comments Raw converted Thresholds RES[1:0] data, left aligned 00: 12-bit DATA[11:0] LT[11:0] and HT[11:0] 01: 10-bit DATA[11:2],00 LT[11:0] and HT[11:0] The user must configure LT1[1:0] and HT1[1:0] to “00” The user must configure LT1[3:0] and HT1[3:0] to 10: 8-bit DATA[11:4],0000...
Page 328: Figure 50. Adc_Awd1_Out Signal Generation
Analog-to-digital converter (ADC) RM0367 ADC_AWD1_OUT is activated when the analog watchdog is enabled: • ADC_AWD1_OUT is set when a guarded conversion is outside the programmed thresholds. • ADC_AWD1_OUT is reset after the end of the next guarded conversion which is inside the programmed thresholds.
Page 329: Analog Watchdog Threshold Control
RM0367 Analog-to-digital converter (ADC) Figure 51. ADC_AWD1_OUT signal generation (AWD flag not cleared by software) ADC STATE Conversion1 Conversion2 Conversion3 Conversion4 Conversion5 Conversion6 Conversion7 inside outside inside outside outside outside inside EOC FLAG not cleared by SW AWD FLAG ADC_AWD1_OUT - Converted channels: 1,2,3,4,5,6,7 - Guarded converted channels: 1,2,3,4,5,6,7 MSv65327V1...
Page 330: Oversampler
Analog-to-digital converter (ADC) RM0367 Figure 53. Analog watchdog threshold update ADC state Conversion Conversion Conversion Conversion Threshould updated LT, HT XXXX XXXY XXXZ Masked Active Active Comparison MSv65329V1 14.8 Oversampler The oversampling unit performs data preprocessing to offload the CPU. It can handle multiple conversions and average them into a single data with increased data width, up to 16-bit.
Page 331: Table 66. Maximum Output Results Vs N And M. Grayed Values Indicates Truncation
RM0367 Analog-to-digital converter (ADC) Figure 54. 20-bit to 16-bit result truncation Raw 20-bit data Shifting Truncation and rounding MS31928V2 Figure 55 gives a numerical example of the processing, from a raw 20-bit accumulated data to the final 16-bit result. Figure 55. Numerical example with 5-bits shift and rounding Raw 20-bit data: Final result after 5-bits shift and rounding to nearest...
Page 332: Adc Operating Modes Supported When Oversampling
Analog-to-digital converter (ADC) RM0367 sequence. New data are provided every N conversion, with an equivalent delay equal to N x = N x (t ). The flags features are raised as following: CONV SMPL • the end of the sampling phase (EOSMP) is set after each sampling phase •...
Page 333: Temperature Sensor And Internal Reference Voltage
ADC V [17] input channel. REFINT The precise voltage of V is individually measured for each part by ST during REFINT production test and stored in the system memory area. It is accessible in read-only mode. Figure 57 shows the block diagram of connections between the temperature sensor, the internal voltage reference and the ADC.
Page 334: Main Features
Analog-to-digital converter (ADC) RM0367 Main features • Supported temperature range: –40 to 125 °C • Linearity: ±2 °C max., precision depending on calibration Figure 57. Temperature sensor and V channel block diagram REFINT TSEN control bit V SENSE Temperature ADC V [18] sensor converted...
Page 335: Calculating The Actual V
RM0367 Analog-to-digital converter (ADC) Note: The sensor has a startup time after waking from power down mode before it can output at the correct level. The ADC also has a startup time after power-on, so to minimize SENSE the delay, the ADEN and TSEN bits should be set at the same time. Calculating the actual V voltage using the internal reference voltage The V...
Page 336: Vlcd Voltage Monitoring
Analog-to-digital converter (ADC) RM0367 14.10 voltage monitoring The VLCDEN bit in the ADC_CCR register allows to measure the LCD supply voltage on the VLCD pin. As the V voltage can be higher than V , to ensure the correct operation of the ADC, the VLCD pin is internally connected to a bridge divider.
Page 337: Adc Registers
RM0367 Analog-to-digital converter (ADC) 14.12 ADC registers Refer to Section 1.2 for a list of abbreviations used in register descriptions. 14.12.1 ADC interrupt and status register (ADC_ISR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res.
Page 338: Adc Interrupt Enable Register (Adc_Ier)
Analog-to-digital converter (ADC) RM0367 Bit 2 EOC: End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register.
Page 339 RM0367 Analog-to-digital converter (ADC) Bit 7 AWDIE: Analog watchdog interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. 0: Analog watchdog interrupt disabled 1: Analog watchdog interrupt enabled Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
Page 340: Adc Control Register (Adc_Cr)
Analog-to-digital converter (ADC) RM0367 14.12.3 ADC control register (ADC_CR) Address offset: 0x08 Reset value: 0x0000 0000 ADVR ADCAL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EGEN ADSTA Res. Res. Res. Res. Res. Res. Res.
Page 341 RM0367 Analog-to-digital converter (ADC) Bit 2 ADSTART: ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration).
Page 342: Adc Configuration Register 1 (Adc_Cfgr1)
Analog-to-digital converter (ADC) RM0367 14.12.4 ADC configuration register 1 (ADC_CFGR1) Address offset: 0x0C Reset value: 0x0000 0000 Res. AWDCH[4:0] Res. Res. AWDEN AWDSGL Res. Res. Res. Res. Res. DISCEN SCAND DMAC AUTOFF WAIT CONT OVRMOD EXTEN[1:0] Res. EXTSEL[2:0] ALIGN RES[1:0] DMAEN Bit 31 Reserved, must be kept at reset value.
Page 343 RM0367 Analog-to-digital converter (ADC) Bit 16 DISCEN: Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. 0: Discontinuous mode disabled 1: Discontinuous mode enabled Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1.
Page 344 Analog-to-digital converter (ADC) RM0367 Bits 8:6 EXTSEL[2:0]: External trigger selection These bits select the external event used to trigger the start of conversion (refer to Table 60: External triggers for details): 000: TRG0 001: TRG1 010: TRG2 011: TRG3 100: TRG4 101: TRG5 110: TRG6 111: TRG7...
Page 345 RM0367 Analog-to-digital converter (ADC) Bit 2 SCANDIR: Scan sequence direction This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. 0: Upward scan (from CHSEL0 to CHSEL18) 1: Backward scan (from CHSEL18 to CHSEL0) Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
Page 346: Adc Configuration Register 2 (Adc_Cfgr2)
Analog-to-digital converter (ADC) RM0367 14.12.5 ADC configuration register 2 (ADC_CFGR2) Address offset: 0x10 Reset value: 0x0000 0000 CKMODE[1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TOVS OVSS[3:0] OVSR[2:0] Res.
Page 347: Adc Sampling Time Register (Adc_Smpr)
RM0367 Analog-to-digital converter (ADC) Bits 4:2 OVSR[2:0]: Oversampling ratio This bit filed defines the number of oversampling ratio. 000: 2x 001: 4x 010: 8x 011: 16x 100: 32x 101: 64x 110: 128x 111: 256x Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
Page 348: Adc Watchdog Threshold Register (Adc_Tr)
Analog-to-digital converter (ADC) RM0367 14.12.7 ADC watchdog threshold register (ADC_TR) Address offset: 0x20 Reset value: 0x0FFF 0000 Res. Res. Res. Res. HT[11:0] Res. Res. Res. Res. LT[11:0] Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 HT[11:0]: Analog watchdog higher threshold These bits are written by software to define the higher threshold for the analog watchdog.
Page 349: Adc Data Register (Adc_Dr)
RM0367 Analog-to-digital converter (ADC) Bits 31:19 Reserved, must be kept at reset value. Bits 18:0 CHSELx: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 36: ADC connectivity for ADC inputs connected to external channels and internal sources.
Page 350: Adc Common Configuration Register (Adc_Ccr)
Analog-to-digital converter (ADC) RM0367 Bits 31:7 Reserved, must be kept at reset value. Bits 6:0 CALFACT[6:0]: Calibration factor These bits are written by hardware or by software. – Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors.
Page 351: Adc Register Map
RM0367 Analog-to-digital converter (ADC) Bit 22 VREFEN: V enable REFINT This bit is set and cleared by software to enable/disable the V REFINT 0: V disabled REFINT 1: V enabled REFINT Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
Page 352 Analog-to-digital converter (ADC) RM0367 Table 68. ADC register map and reset values (continued) Offset Register ADC_CFGR2 0x10 Reset value ADC_SMPR [2:0] 0x14 Reset value 0x18 Reserved Reserved 0x1C Reserved Reserved ADC_TR HT[11:0] LT[11:0] 0x20 Reset value 0x24 Reserved Reserved ADC_CHSELR 0x28 Reset value 0x2C...
Page 353: Digital-To-Analog Converter (Dac)
RM0367 Digital-to-analog converter (DAC) Digital-to-analog converter (DAC) 15.1 Introduction The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned.
Page 354: Table 69. Dac Pins
Digital-to-analog converter (DAC) RM0367 Figure 58. DAC block diagram DAC control register TSELx[2:0] bits SWTRIGx TIM6_TRGO DMAENx TIM7_TRGO TIM3_TRGO TIM3_CH3 TIM21_TRGO TIM2_TRGO EXTI_9 DM A req ue stx TENx 12-bit DHRx Control logic BOFF 12-bit DORx 12-bit Digital-to-analog DAC_ OU T1/2 converterx REF+ MS33718V3...
Page 355: Dac Output Buffer Enable
RM0367 Digital-to-analog converter (DAC) 15.3 DAC output buffer enable The DAC integrates two output buffers that can be used to reduce the output impedance and to drive external loads directly without having to add an external operational amplifier. The DAC channel output buffer can be enabled and disabled through the BOFF1 bit in the DAC_CR register.
Page 356: Independent Trigger With Single Lfsr Generation
Digital-to-analog converter (DAC) RM0367 register is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR register is set) and a trigger occurs, the transfer is performed three PCLK1 clock cycles later. When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage becomes available after a time t that depends on the power supply voltage and the SETTLING...
Page 357: Dac Output Voltage
RM0367 Digital-to-analog converter (DAC) For code example, refer to A.9.2: Independent trigger with single triangle generation code example. 15.5.3 DAC output voltage Digital inputs are converted to output voltages on a linear conversion between 0 and V REF+ The analog output voltages on each DAC channel pin are determined by the following equation: ×...
Page 358: Dual-Mode Functional Description
Digital-to-analog converter (DAC) RM0367 15.6 Dual-mode functional description 15.6.1 DAC data format In Dual DAC channel mode, there are three possibilities: • 8-bit right alignment: data for DAC channel1 to be loaded in the DAC_DHR8RD [7:0] bits (stored in the DHR1[11:4] bits) and data for DAC channel2 to be loaded in the DAC_DHR8RD [15:8] bits (stored in the DHR2[11:4] bits) •...
Page 359: Independent Trigger Without Wave Generation
RM0367 Digital-to-analog converter (DAC) Independent trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: Set the two DAC channel trigger enable bits TEN1 and TEN2 Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD)
Page 360: Independent Trigger With Single Triangle Generation
Digital-to-analog converter (DAC) RM0367 Independent trigger with single triangle generation To configure the DAC in this conversion mode (refer to Section 15.8: Triangle-wave generation), the following sequence is required: Set the DAC channelx trigger enable TENx bits. Configure different trigger sources by setting different values in the TSELx[2:0] bits Configure the DAC channelx WAVEx[1:0] bits as “1x”...
Page 361: Simultaneous Trigger With Single Lfsr Generation
RM0367 Digital-to-analog converter (DAC) Simultaneous trigger with single LFSR generation To configure the DAC in this conversion mode (refer to Section 15.7: Noise generation), the following sequence is required: Set the two DAC channel trigger enable bits TEN1 and TEN2 Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits Configure the two DAC channel WAVEx[1:0] bits as “01”...
Page 362: Simultaneous Trigger With Different Triangle Generation
Digital-to-analog converter (DAC) RM0367 Simultaneous trigger with different triangle generation To configure the DAC in this conversion mode ‘refer to Section 15.8: Triangle-wave generation), the following sequence is required: Set the DAC channelx trigger enable TENx bits. Configure the same trigger source for DAC channelx by setting the same value in the TSELx[2:0] bits Configure the DAC channelx WAVEx[1:0] bits as “1x”...
Page 363: Triangle-Wave Generation
RM0367 Digital-to-analog converter (DAC) It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits. Figure 63. DAC conversion (SW trigger enabled) with LFSR wave generation APB1_CLK 0x00 0xD55 0xAAA SWTRIG ai14714b Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the DAC_CR register.
Page 364: Dma Request
Digital-to-analog converter (DAC) RM0367 Figure 65. DAC conversion (SW trigger enabled) with triangle wave generation APB1_CLK 0xABE 0xABE 0xABF 0xAC0 SWTRIG ai14716b Note: The DAC trigger must be enabled for triangle generation by setting the TENx bit in the DAC_CR register. The MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot be changed.
Page 365: Dac Registers
RM0367 Digital-to-analog converter (DAC) 15.10 DAC registers Refer to Section 1.2 on page 52 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 15.10.1 DAC control register (DAC_CR) Address offset: 0x00 Reset value: 0x0000 0000 DMAU Res.
Page 366 Digital-to-analog converter (DAC) RM0367 Bits 23:22 WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 00: wave generation disabled 01: Noise wave generation enabled 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) These bits are available only in dual mode when wave generation is supported.
Page 367 RM0367 Digital-to-analog converter (DAC) Bit 12 DMAEN1: DAC channel1 DMA enable This bit is set and cleared by software. 0: DAC channel1 DMA mode disabled 1: DAC channel1 DMA mode enabled Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode.
Page 368 Digital-to-analog converter (DAC) RM0367 Bit 2 TEN1: DAC channel1 trigger enable This bit is set and cleared by software to enable/disable DAC channel1 trigger. 0: DAC channel1 trigger disabled and data written into the DAC_DHRx register are transferred one APB1 clock cycle later to the DAC_DOR1 register 1: DAC channel1 trigger enabled and data from the DAC_DHRx register are transferred three APB1 clock cycles later to the DAC_DOR1 register Note: When software trigger is selected, the transfer from the DAC_DHRx register to the...
Page 369: Dac Software Trigger Register (Dac_Swtrigr)
RM0367 Digital-to-analog converter (DAC) 15.10.2 DAC software trigger register (DAC_SWTRIGR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 370: Dac Channel1 12-Bit Left-Aligned Data Holding Register
Digital-to-analog converter (DAC) RM0367 15.10.4 DAC channel1 12-bit left-aligned data holding register (DAC_DHR12L1) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DACC1DHR[11:0] Res. Res. Res. Bits 31:16 Reserved, must be kept at reset value.
Page 371: Dac Channel2 12-Bit Left-Aligned Data Holding Register
RM0367 Digital-to-analog converter (DAC) Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 15.10.7 DAC channel2 12-bit left-aligned data holding register (DAC_DHR12L2) Address offset: 0x18 Reset value: 0x0000 0000...
Page 372: Dual Dac 12-Bit Right-Aligned Data Holding Register
Digital-to-analog converter (DAC) RM0367 15.10.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) Address offset: 0x20 Reset value: 0x0000 0000 Res. Res. Res. Res. DACC2DHR[11:0] Res. Res. Res. Res. DACC1DHR[11:0] Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
Page 373: Dac Channel1 Data Output Register (Dac_Dor1)
RM0367 Digital-to-analog converter (DAC) DACC2DHR[7:0] DACC1DHR[7:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1.
Page 374 Digital-to-analog converter (DAC) RM0367 Res. Res. DMAUDR2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rc_w1 Res. Res. DMAUDR1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rc_w1 Bits 31:30 Reserved, must be kept at reset value. Bit 29 DMAUDR2: DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).
Page 375: 15.10.15 Dac Register Map
RM0367 Digital-to-analog converter (DAC) 15.10.15 DAC register map Table 71 summarizes the DAC registers. Table 71. DAC register map and reset values Register Offset name DAC_CR 0x00 Reset value DAC_ SWTRIGR 0x04 Reset value DAC_ DACC1DHR[11:0] DHR12R1 0x08 Reset value DAC_ DACC1DHR[11:0] DHR12L1...
Page 376 Digital-to-analog converter (DAC) RM0367 Table 71. DAC register map (continued)and reset values (continued) Register Offset name DAC_SR 0x34 Reset value Refer to Section 2.2 on page 58 for the register boundary addresses. 376/1043 RM0367 Rev 7...
Page 377: Comparator (Comp)
Comparator (COMP) 16.1 Introduction STM32L0x3 devices embed two ultra-low-power comparators COMP1, and COMP2 that can be used either as standalone devices (all terminal are available on I/Os) or combined with the timers. The comparators can be used for a variety of functions including: •...
Page 378: Comp Functional Description
Comparator (COMP) RM0367 16.3 COMP functional description 16.3.1 COMP block diagram The block diagram of the comparators is shown in Figure 66: Comparator 1 and 2 block diagrams. Figure 66. Comparator 1 and 2 block diagrams COMP1INNSEL COMP1 VREFINT COMP1POLARITY Wakeup EXTI line 21 PA4 (DAC1)
Page 379: Comp Reset And Clocks
RM0367 Comparator (COMP) 16.3.3 COMP reset and clocks The COMP clock provided by the clock controller is synchronous with the PCLK (APB clock). There is no clock enable control bit provided in the RCC controller. Reset and clock enable bits are common for COMP and SYSCFG. Important: The polarity selection logic and the output redirection to the port works independently from the PCLK clock.
Page 380 Comparator (COMP) RM0367 COMP1 COMP1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LOCK VALUE COMP1 COMP1 COMP1 COMP1INN COMP1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. POLARITY LPTIMIN1 Bit 31 COMP1LOCK: COMP1_CSR register lock bit This bit is set by software and cleared by a hardware system reset.
Page 381: Comparator 2 Control And Status Register (Comp2_Csr)
RM0367 Comparator (COMP) Bits 5:4 COMP1INNSEL: Comparator 1 Input Minus connection configuration bit These bits are set and cleared by software (only if COMP1LOCK not set). They select which input is connected with the Input Minus of comparator 1 00: VREFINT 01: PA0 10: DAC1/PA4 11: DAC2/PA5...
Page 382 Comparator (COMP) RM0367 Bit 13 COMP2LPTIMIN1: Comparator 2 LPTIM input 1 propagation bit This bit is set and cleared by software (assuming COMP2LOCK not set). It sends COMP2VALUE to LPTIM input 1. 0: Comparator 2 output gated 1: Comparator 2 output sent to LPTIM input 1 Note: COMP2LPTIMIN1 and COMP2LPTIMIN2 cannot both be set to ‘1’.
Page 383: Comp Register Map
RM0367 Comparator (COMP) 16.5.3 COMP register map The following table summarizes the comparator registers. The comparator registers share SYSCFG peripheral register base addresses. Table 72. COMP register map and reset values Offset Register COMP1_CSR 0x18 Reset value COMP2_CSR 0x1C Reset value Refer to Section 2.2 on page 58 for the register boundary addresses.
Page 384: Liquid Crystal Display Controller (Lcd)
Liquid crystal display controller (LCD) RM0367 Liquid crystal display controller (LCD) 17.1 Introduction The LCD controller is a digital controller/driver for monochrome passive liquid crystal display (LCD) with up to 8 common terminals and up to 52 segment terminals to drive 208 (4x52) or 384 (8x48) LCD picture elements (pixels).
Page 385: Lcd Main Features
RM0367 Liquid crystal display controller (LCD) 17.2 LCD main features • Highly flexible frame rate control. • Supports Static, 1/2, 1/3, 1/4 and 1/8 duty. • Supports Static, 1/2, 1/3 and 1/4 bias. • Double buffered memory allows data in LCD_RAM registers to be updated at any time by the application firmware without affecting the integrity of the data displayed.
Page 386: Lcd Implementation
Liquid crystal display controller (LCD) RM0367 17.3 LCD implementation Table 73. Implementation Products Segments terminals Category 5 devices 52 segments Category 3 devices 32 segments 17.4 LCD functional description 17.4.1 General description The LCD controller has five main blocks (see Figure 67): Figure 67.
Page 387: Frequency Generator
RM0367 Liquid crystal display controller (LCD) The frequency generator allows you to achieve various LCD frame rates starting from an LCD input clock frequency (LCDCLK) which can vary from 32 kHz up to 1 MHz. 3 different clock sources can be used to provide the LCD clock (LCDCLK/RTCCLK): •...
Page 388: Common Driver
Liquid crystal display controller (LCD) RM0367 Table 74. Example of frame rate calculation (continued) LCDCLK PS[3:0] DIV[3:0] Ratio Duty frame 1.00 MHz 2432 102.80 Hz 1.00 MHz 3328 100.16 Hz 1.00 MHz 4864 102.80 Hz 1.00 MHz 9728 static 102.80 Hz The frame frequency must be selected to be within a range of around ~30 Hz to ~100 Hz and is a compromise between power consumption and the acceptable refresh rate.
Page 389: Com Signal Duty
RM0367 Liquid crystal display controller (LCD) Figure 68. 1/3 bias, 1/4 duty Odd frame Even frame 2/3 V 1/3 V Com active Com inactive Com inactive Com inactive Com active Com inactive Com inactive Com inactive 2/3 V 1/3 V Com active Com active Com inactive Com inactive...
Page 390: Figure 69. Static Duty Case 1
Liquid crystal display controller (LCD) RM0367 Figure 69. Static duty case 1 Odd frame Even frame Odd frame Even frame COM0 SEG0 SEG1 COM0 SEG0 COM0 SEG1 MS33439V1 In each frame there is only one phase, this is why f is equal to f .
Page 391: To 1 Mux
RM0367 Liquid crystal display controller (LCD) In this mode, the segment terminals are multiplexed and each of them control four pixels. A pixel is activated only when both of its corresponding SEG and COM lines are active in the same phase. In case of 1/4 duty, to deactivate pixel 0 connected to COM[0] the SEG[0] needs to be inactive during the phase 0 when COM[0] is active.
Page 392: Figure 72. 1/3 Duty, 1/3 Bias
Liquid crystal display controller (LCD) RM0367 The SEG[n] pin is driven to V in phase 0 of the even frame. If pixel n is inactive then the SEG[n] pin is driven to 2/3 (2/4) V in the odd frame or 1/3 (2/4) V in the even frame (current inversion in V pad) (see...
Page 393: Figure 73. 1/4 Duty, 1/3 Bias
RM0367 Liquid crystal display controller (LCD) Figure 73. 1/4 duty, 1/3 bias 3/3 V 2/3 V COM0 1/3 V Liquid crystal display 0/3 V and terminal connection 3/3 V COM3 2/3 V COM1 1/3 V 0/3 V COM2 3/3 V 2/3 V COM2 COM1...
Page 394: Figure 74. 1/8 Duty, 1/4 Bias
Liquid crystal display controller (LCD) RM0367 Figure 74. 1/8 duty, 1/4 bias Liquid crystal display 4/4 V and terminal connection 3/4 V COM0 2/4 V COM7 1/4 V 0/4 V COM5 COM6 4/4 V 3/4 V COM4 COM1 2/4 V COM3 COM1 1/4 V...
Page 395: Blink
RM0367 Liquid crystal display controller (LCD) Blink The segment driver also implements a programmable blink feature to allow some pixels to continuously switch on at a specific frequency. The blink mode can be configured by the BLINK[1:0] bits in the LCD_FCR register, making possible to blink up to 1, 2, 4, 8 or all pixels (see Section 17.7.2: LCD frame control register (LCD_FCR)).
Page 396: Lcd Intermediate Voltages
Liquid crystal display controller (LCD) RM0367 LCD intermediate voltages The LCD intermediate voltage levels are generated through an internal resistor divider network as shown in Figure The LCD voltage generator issues intermediate voltage levels between V and V • 1/3 V and 2/3 V in case of 1/3 bias •...
Page 397: Figure 75. Lcd Voltage Control
RM0367 Liquid crystal display controller (LCD) Figure 75. LCD voltage control 3/4 x V LCDRail3 2/3 x V LCDRail2 1/2 x V 1/3 x V LCDRail1 1/4 x V BIAS[1] STATIC MS33422V2 1. R and R are the low value resistance network and the high value resistance network, respectively. The R divider can be always switched on using the HD bit in the LCD_FCR configuration register (see...
Page 398: External Decoupling
Liquid crystal display controller (LCD) RM0367 External decoupling Devices with V rails decoupling capability (see device datasheets) allow adding decoupling capacitors on the VLCD intermediate voltage rails that available on LCD_VLCD1, LCD_VLCD2 and LCD_VLCD3 for stabilization purpose (see Figure 75). Spikes might be observed when the voltage applied to the pixel is alternating.
Page 399: Double Buffer Memory
RM0367 Liquid crystal display controller (LCD) 17.4.6 Double buffer memory Using its double buffer memory the LCD controller ensures the coherency of the displayed information without having to use interrupts to control LCD_RAM modification. The application software can access the first buffer level (LCD_RAM) through the APB interface.
Page 400: Summary Of Com And Seg Functions Versus Duty And Remap
Liquid crystal display controller (LCD) RM0367 Summary of COM and SEG functions versus duty and remap All the possible ways of multiplexing the COM and SEG functions are described in Table Figure 77 gives examples showing the signal connections to the external pins. Table 77.
Page 401 RM0367 Liquid crystal display controller (LCD) Table 77. Remapping capability (continued) Configuration bits QFP64/ BGA100/ BGA64 Output pin Function LQFP100 DUTY MUX_SEG COM3 not used COM[2:0] COM[2:0] 52x3 SEG[51:48]/SEG[31:28]/COM[7:4] SEG[51:48] SEG[47:0] SEG[47:0] COM3 not used COM[2:0] COM[2:0] SEG[51:48]/SEG[31:28]/COM[7:4] SEG[31:28] 48x3 SEG[47:32] SEG[47:32] SEG[31:28]...
Page 402 Liquid crystal display controller (LCD) RM0367 Table 77. Remapping capability (continued) Configuration bits QFP64/ BGA100/ BGA64 Output pin Function LQFP100 DUTY MUX_SEG COM[3:2] not used COM[1:0] COM[1:0] 28x2 SEG[51:48]/SEG[31:28]/COM[7:4] not used SEG[27:0] SEG[27:0] COM[3:2] not used COM[1:0] COM[1:0] 32x2 SEG[51:48]/SEG[31:28]/COM[7:4] SEG[31:28] SEG[27:0] SEG[27:0]...
Page 403: Figure 77. Seg/Com Mux Feature Example
RM0367 Liquid crystal display controller (LCD) Figure 77. SEG/COM mux feature example LCD CONTROLLER SEG[51] SEG[31] SEG DRIVER LCD_SEG[51] COM[7] COM DRIVER DUTY ≠ 1/8 and MUX_SEG = 0 LCD CONTROLLER SEG[51] SEG[31] SEG DRIVER LCD_SEG[31] COM[7] COM DRIVER DUTY ≠ 1/8 and MUX_SEG = 1 LCD CONTROLLER SEG[51] SEG[31]...
Page 404: Flowchart
Liquid crystal display controller (LCD) RM0367 17.4.8 Flowchart Figure 78. Flowchart example START INIT - Enable the GPIO port clocks - Configure the LCD GPIO pins as alternate functions - Configure LCD controller according to the Display to be driven: - Load the initial data to be displayed into LCD_RAM and set the UDR bit in the LCD_SR register...
Page 405: Lcd Low-Power Modes
RM0367 Liquid crystal display controller (LCD) 17.5 LCD low-power modes the LCD controller can be displayed in Stop mode or can be fully disabled to reduce power consumption. Table 78. LCD behavior in low-power modes Mode Description Stop The LCD is still active Standby The LCD is not active 17.6...
Page 406: Lcd Registers
Liquid crystal display controller (LCD) RM0367 17.7 LCD registers The peripheral registers have to be accessed by words (32-bit). 17.7.1 LCD control register (LCD_CR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 407: Lcd Frame Control Register (Lcd_Fcr)
RM0367 Liquid crystal display controller (LCD) Note: The VSEL, MUX_SEG,BIAS, and DUTY bits are write-protected when the LCD is enabled (ENS bit in LCD_SR to 1). 17.7.2 LCD frame control register (LCD_FCR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res.
Page 408 Liquid crystal display controller (LCD) RM0367 Bits 12:10 CC[2:0]: Contrast control These bits specify one of the V maximum voltages (independent of V ). It ranges from 2.60 V to 3.51V. 000: V LCD0 001: V LCD1 010: V LCD2 011: V LCD3 100: V...
Page 409: Lcd Status Register (Lcd_Sr)
RM0367 Liquid crystal display controller (LCD) Bit 2 Reserved, must be kept at reset value Bit 1 SOFIE: Start of frame interrupt enable This bit is set and cleared by software. 0: LCD Start of Frame interrupt disabled 1: LCD Start of Frame interrupt enabled Bit 0 HD: High drive enable This bit is written by software to enable a low resistance divider.
Page 410: Lcd Clear Register (Lcd_Clr)
Liquid crystal display controller (LCD) RM0367 Bit 3 UDD: Update Display Done This bit is set by hardware. It is cleared by writing 1 to the UDDC bit in the LCD_CLR register. The bit set has priority over the clear. 0: No event 1: Update Display Request done.
Page 411: Lcd Display Memory (Lcd_Ram)
RM0367 Liquid crystal display controller (LCD) Bits 31:4 Reserved, must be kept at reset value Bit 3 UDDC: Update display done clear This bit is written by software to clear the UDD flag in the LCD_SR register. 0: No effect 1: Clear UDD flag Bit 2 Reserved, must be kept at reset value Bit 1 SOFC: Start of frame flag clear...
Page 412: Lcd Register Map
Liquid crystal display controller (LCD) RM0367 17.7.6 LCD register map The following table summarizes the LCD registers. Table 80. LCD register map and reset values Register DUTY LCD_CR [2:0] 0x00 Reset value DEAD PS[3:0] DIV[3:0] LCD_FCR [2:0] [2:0] [2:0] 0x04 Reset value LCD_SR 0x08...
Page 413 RM0367 Liquid crystal display controller (LCD) Table 80. LCD register map and reset values (continued) Register 0x34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCD_RAM (COM4) 0x38...
Page 414: Touch Sensing Controller (Tsc)
Touch sensing controller (TSC) RM0367 Touch sensing controller (TSC) 18.1 Introduction The touch sensing controller provides a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect finger presence near an electrode that is protected from direct touch by a dielectric (for example glass, plastic).
Page 415: Tsc Functional Description
RM0367 Touch sensing controller (TSC) 18.3 TSC functional description 18.3.1 TSC block diagram The block diagram of the touch sensing controller is shown in Figure Figure 79. TSC block diagram SYNC Pulse generator G1_IO1 HCLK Clock G1_IO2 prescalers G1_IO3 Spread spectrum G1_IO4 G2_IO1 G2_IO2...
Page 416: Figure 80. Surface Charge Transfer Analog I/O Group Structure
Touch sensing controller (TSC) RM0367 Figure 80. Surface charge transfer analog I/O group structure Analog I/O group Electrode 1 Gx_IO1 Gx_IO2 Electrode 2 Gx_IO3 Electrode 3 Gx_IO4 MSv30930V2 Note: Gx_IOy where x is the analog I/O group number and y the GPIO number within the selected group.
Page 417: Reset And Clocks
RM0367 Touch sensing controller (TSC) Table 81. Acquisition sequence summary Gx_IO1 Gx_IO2 Gx_IO3 Gx_IO4 State State description (channel) (sampling) (channel) (channel) Output open- Input floating drain low with Input floating with analog switch Discharge all C with analog analog switch closed switch closed closed...
Page 418: Charge Transfer Acquisition Sequence
Touch sensing controller (TSC) RM0367 The Reset and Clock Controller (RCC) provides dedicated bits to enable the touch sensing controller clock and to reset this peripheral. For more information, refer to Section 7: Reset and clock control (RCC). 18.3.4 Charge transfer acquisition sequence An example of a charge transfer acquisition sequence is detailed in Figure Figure 82.
Page 419: Spread Spectrum Feature
RM0367 Touch sensing controller (TSC) 18.3.5 Spread spectrum feature The spread spectrum feature allows to generate a variation of the charge transfer frequency. This is done to improve the robustness of the charge transfer acquisition in noisy environments and also to reduce the induced emission. The maximum frequency variation is in the range of 10% to 50% of the nominal charge transfer period.
Page 420: Sampling Capacitor I/O And Channel I/O Mode Selection
Touch sensing controller (TSC) RM0367 18.3.7 Sampling capacitor I/O and channel I/O mode selection To allow the GPIOs to be controlled by the touch sensing controller, the corresponding alternate function must be enabled through the standard GPIO registers and the GPIOxAFR registers.
Page 421: Acquisition Mode
RM0367 Touch sensing controller (TSC) 18.3.8 Acquisition mode The touch sensing controller offers two acquisition modes: • Normal acquisition mode: the acquisition starts as soon as the START bit in the TSC_CR register is set. • Synchronized acquisition mode: the acquisition is enabled by setting the START bit in the TSC_CR register but only starts upon the detection of a falling edge or a rising edge and high level on the SYNC input pin.
Page 422: Tsc Low-Power Modes
Touch sensing controller (TSC) RM0367 18.4 TSC low-power modes Table 84. Effect of low-power modes on TSC Mode Description No effect Sleep TSC interrupts cause the device to exit Sleep mode. Stop TSC registers are frozen The TSC stops its operation until the Stop or Standby mode is exited. Standby 18.5 TSC interrupts...
Page 423: Tsc Registers
RM0367 Touch sensing controller (TSC) 18.6 TSC registers Refer to Section 1.2 on page 52 of the reference manual for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by words (32-bit). 18.6.1 TSC control register (TSC_CR) Address offset: 0x00 Reset value: 0x0000 0000 CTPH[3:0]...
Page 424 Touch sensing controller (TSC) RM0367 Bit 16 SSE: Spread spectrum enable This bit is set and cleared by software to enable/disable the spread spectrum feature. 0: Spread spectrum disabled 1: Spread spectrum enabled Note: This bit must not be modified when an acquisition is ongoing. Bit 15 SSPSC: Spread spectrum prescaler This bit is set and cleared by software.
Page 425: Tsc Interrupt Enable Register (Tsc_Ier)
RM0367 Touch sensing controller (TSC) Bit 2 AM: Acquisition mode This bit is set and cleared by software to select the acquisition mode. 0: Normal acquisition mode (acquisition starts as soon as START bit is set) 1: Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) Note: This bit must not be modified when an acquisition is ongoing.
Page 426: Tsc Interrupt Clear Register (Tsc_Icr)
Touch sensing controller (TSC) RM0367 18.6.3 TSC interrupt clear register (TSC_ICR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 427: Tsc Interrupt Status Register (Tsc_Isr)
RM0367 Touch sensing controller (TSC) 18.6.4 TSC interrupt status register (TSC_ISR) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 428: Tsc I/O Analog Switch Control Register (Tsc_Ioascr)
Touch sensing controller (TSC) RM0367 18.6.6 TSC I/O analog switch control register (TSC_IOASCR) Address offset: 0x18 Reset value: 0x0000 0000 G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1 G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1 Bits 31:0 Gx_IOy: Gx_IOy analog switch enable These bits are set and cleared by software to enable/disable the Gx_IOy analog switch.
Page 429: Tsc I/O Channel Control Register (Tsc_Ioccr)
RM0367 Touch sensing controller (TSC) 18.6.8 TSC I/O channel control register (TSC_IOCCR) Address offset: 0x28 Reset value: 0x0000 0000 G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1 G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1 Bits 31:0 Gx_IOy: Gx_IOy channel mode These bits are set and cleared by software to configure the Gx_IOy as a channel I/O.
Page 430: Tsc I/O Group X Counter Register (Tsc_Iogxcr)
Touch sensing controller (TSC) RM0367 18.6.10 TSC I/O group x counter register (TSC_IOGxCR) x represents the analog I/O group number. Address offset: 0x30 + 0x04 * x, (x = 1..8) Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res.
Page 431: Tsc Register Map
RM0367 Touch sensing controller (TSC) 18.6.11 TSC register map Table 86. TSC register map and reset values Offset Register CTPH[3:0] CTPL[3:0] SSD[6:0] TSC_CR [2:0] 0x0000 Reset value TSC_IER 0x0004 Reset value TSC_ICR 0x0008 Reset value TSC_ISR 0x000C Reset value TSC_IOHCR 0x0010 Reset value 0x0014...
Page 432 Touch sensing controller (TSC) RM0367 Table 86. TSC register map and reset values (continued) Offset Register CNT[13:0] TSC_IOG3CR 0x003C Reset value CNT[13:0] TSC_IOG4CR 0x0040 Reset value CNT[13:0] TSC_IOG5CR 0x0044 Reset value CNT[13:0] TSC_IOG6CR 0x0048 Reset value CNT[13:0] TSC_IOG7CR 0x004C Reset value CNT[13:0] TSC_IOG8CR 0x0050...
Page 433: Aes Hardware Accelerator (Aes)
RM0367 AES hardware accelerator (AES) AES hardware accelerator (AES) 19.1 Introduction The AES hardware accelerator (AES) encrypts or decrypts data, using an algorithm and implementation fully compliant with the advanced encryption standard (AES) defined in Federal information processing standards (FIPS) publication 197. Multiple chaining modes are supported (ECB, CBC, CTR), for key size of 128 bits.
Page 434: Aes Implementation
AES hardware accelerator (AES) RM0367 19.3 AES implementation The device has a single instance of AES peripheral. 19.4 AES functional description 19.4.1 AES block diagram Figure 84 shows the block diagram of AES. Figure 84. AES block diagram 32-bit access Banked registers AES_KEYRx 32-bit...
Page 435: Aes Cryptographic Core
RM0367 AES hardware accelerator (AES) 19.4.3 AES cryptographic core Overview The AES cryptographic core consists of the following components: • AES algorithm (AEA) • key input • initialization vector (IV) input The AES core works on 128-bit data blocks (four words) with 128-bit key length. Depending on the chaining mode, the AES requires zero or one 96-bit initialization vector IV (and a 32- bit counter field).
Page 436: Electronic Codebook (Ecb) Mode
AES hardware accelerator (AES) RM0367 Note: The chaining mode may be changed only when AES is disabled (bit EN of the AES_CR register set). Principle of each AES chaining mode is provided in the following subsections. Detailed information is in dedicated sections, starting from Section 19.4.8: AES basic chaining modes (ECB, CBC).
Page 437: Cipher Block Chaining (Cbc) Mode
RM0367 AES hardware accelerator (AES) Cipher block chaining (CBC) mode Figure 86. CBC encryption and decryption principle Encryption Plaintext block 1 Plaintext block 2 Plaintext block 3 initialization vector Encrypt Encrypt Encrypt Ciphertext block 1 Ciphertext block 2 Ciphertext block 3 Decryption Plaintext block 1 Plaintext block 2...
Page 438: Counter (Ctr) Mode
AES algorithm. AES accelerates the execution of the AES-128 cryptographic algorithm in ECB, CBC, and CTR operating modes. Note: For more details on the cryptographic library, refer to the UM1924 user manual “STM32 crypto library” available from www.st.com. 438/1043 RM0367 Rev 7...
Page 439: Initialization Of Aes
RM0367 AES hardware accelerator (AES) Figure 88. STM32 cryptolib AES flowchart example Encryption Decryption Begin Begin AES_x encrypt init AES_x decrypt init Error status Error status success success AES_x encrypt AES_x decrypt append append Data to append Data to append Error status Error status success...
Page 440 AES hardware accelerator (AES) RM0367 For ECB or CBC mode, refer to Section 19.4.6: AES ciphertext stealing and data padding. The second-last and the last block management in these cases is more complex than in the sequence described in this section. Data append through polling This method uses flag polling to control the data append.
Page 441: Aes Decryption Key Preparation
RM0367 AES hardware accelerator (AES) Prepare the last four-word data block (if the data to process does not fill it completely), by padding the remainder of the block with zeros. Configure the DMA controller so as to transfer the data to process from the memory to the AES peripheral input and the processed data from the AES peripheral output to the memory, as described in Section 19.4.13: AES DMA...
Page 442: Aes Ciphertext Stealing And Data Padding
AES hardware accelerator (AES) RM0367 Figure 89. Encryption key derivation for ECB/CBC decryption (Mode 2) Wait until flag CCF = 1 Input phase Output phase (optional) 4 write operations into Computation phase 4 read operations of AES_KEYRx[31:0] AES_KEYRx[31:0] EN = 1 into AES_CR 128-bit derivation key stored into AES_KEYRx EK = encryption key = 4 words (EK3, …...
Page 443: Aes Basic Chaining Modes (Ecb, Cbc)
RM0367 AES hardware accelerator (AES) Figure 90. Example of suspend mode management Message 1 Message 2 128-bit block 1 New higher-priority 128-bit block 2 message 2 to be AES suspend processed sequence 128-bit block 3 128-bit block 1 128-bit block 2 128-bit block 4 AES resume 128-bit block 5...
Page 444: Figure 92. Ecb Decryption
AES hardware accelerator (AES) RM0367 output data block Cx. The ECB encryption continues in this way until the last complete plaintext block is encrypted. Figure 92 illustrates the electronic codebook (ECB) decryption. Figure 92. ECB decryption Block 1 Block 2 AES_DINR (ciphertext C1) AES_DINR (ciphertext C2) Swap...
Page 445: Figure 94. Cbc Decryption
RM0367 AES hardware accelerator (AES) second-block plaintext data P2’ to produce the I2 input data for the AES core to produce the second block of ciphertext data. The chaining of data blocks continues in this way until the last plaintext block in the message is encrypted. If the message size is not a multiple of 128 bits, the final partial data block is encrypted in the way explained in Section 19.4.6: AES ciphertext stealing and data...
Page 446: Ecb/Cbc Encryption Sequence
AES hardware accelerator (AES) RM0367 ECB/CBC encryption sequence The sequence of events to perform an ECB/CBC encryption (more detail in Section 19.4.4): Disable the AES peripheral by clearing the EN bit of the AES_CR register. Select the Mode 1 by to 00 the MODE[1:0] bitfield of the AES_CR register and select ECB or CBC chaining mode by setting the CHMOD[1:0] bitfield of the AES_CR register to 00 or 01, respectively.
Page 447: Suspend/Resume Operations In Ecb/Cbc Modes
RM0367 AES hardware accelerator (AES) Repeat steps 6,7,8 to process all the blocks encrypted with the same key. Figure 96. ECB/CBC decryption (Mode 3) Wait until flag CCF = 1 Input phase Computation phase Output phase 4 write operations into 4 read operations from AES_DINR[31:0] AES_DOUTR[31:0]...
Page 448: Alternative Single Ecb/Cbc Decryption Using Mode 4
AES hardware accelerator (AES) RM0367 To resume the processing of a message, proceed as follows: If DMA is used, configure the DMA controller so as to complete the rest of the FIFO IN and FIFO OUT transfers. Ensure that AES is disabled (the EN bit of the AES_CR must be 0). Restore the AES_CR and AES_KEYRx register setting, using the values of the saved configuration.
Page 449: Ctr Encryption And Decryption
RM0367 AES hardware accelerator (AES) Figure 97. Message construction in CTR mode 16-byte boundaries Zero padding Ciphertext (C) 4-byte boundaries Plaintext (P) Initialization vector (IV) Counter MSv42156V1 The structure of this message is: • A 16-byte initial counter block (ICB), composed of two distinct fields: –...
Page 450: Table 88. Ctr Mode Initialization Vector Definition
AES hardware accelerator (AES) RM0367 Figure 99. CTR decryption Block 1 Block 2 AES_IVRx AES_IVRx Nonce + 32-bit counter Nonce + 32-bit counter (+1) Counter increment (+1) AES_KEYRx (KEY) AES_KEYRx (KEY) Encrypt Encrypt AES_DINR (ciphertext C1) AES_DINR (ciphertext C2) DATATYPE[1:0] DATATYPE[1:0] Swap Swap...
Page 451: Suspend/Resume Operations In Ctr Mode
RM0367 AES hardware accelerator (AES) The sequence of events to perform an encryption or a decryption in CTR chaining mode: Ensure that AES is disabled (the EN bit of the AES_CR must be 0). Select CTR chaining mode by setting to 10 the CHMOD[1:0] bitfield of the AES_CR register.
Page 452: Figure 100. 128-Bit Block Construction With Respect To Data Swap
AES hardware accelerator (AES) RM0367 The data swap type is selected through the DATATYPE[1:0] bitfield of the AES_CR register. The selection applies both to the input and the output of the AES core. For different data swap types, Figure 100 shows the construction of AES processing core input buffer data P127..0, from the input data entered through the AES_DINR register, or the construction of the output data available through the AES_DOUTR register, from the AES...
Page 453: Data Padding
RM0367 AES hardware accelerator (AES) Data padding Figure 100 also gives an example of memory data block padding with zeros such that the zeroed bits after the data swap form a contiguous zone at the MSB end of the AES core input buffer.
Page 454: Data Input Using Dma
AES hardware accelerator (AES) RM0367 Data input using DMA Setting the DMAINEN bit of the AES_CR register enables DMA writing into AES. The AES peripheral then initiates a DMA request during the input phase each time it requires a word to be written to the AES_DINR register.
Page 455: Dma Operation In Different Operating Modes
RM0367 AES hardware accelerator (AES) word to be read from the AES_DOUTR register. It asserts four DMA requests to transfer one 128-bit (four-word) output data block to memory, as shown in Figure 102. Table 91 for recommended DMA configuration. Table 91. DMA channel configuration for AES-to-memory data transfer DMA channel control Recommended configuration register field...
Page 456: Aes Error Management
AES hardware accelerator (AES) RM0367 DMA single requests are generated by AES until it is disabled. So, after the data output phase at the end of processing of a 128-bit data block, AES switches automatically to a new data input phase for the next data block, if any. When the data transferring between AES and memory is managed by DMA, the CCF flag is not relevant and can be ignored (left set) by software.
Page 457: Aes Processing Latency
RM0367 AES hardware accelerator (AES) Figure 103. AES interrupt signal generation CCFIE WRERR Flags in AES_SR register aes_it Bits of AES_CR register ERRIE (goes to NVIC) RDERR ERRIE MSv42162V1 Each AES interrupt source can individually be enabled/disabled, by setting/clearing the corresponding enable bit of the AES_CR register.
Page 458: Aes Registers
AES hardware accelerator (AES) RM0367 19.7 AES registers 19.7.1 AES control register (AES_CR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMAO DMAIN Res. Res. Res.
Page 459 RM0367 AES hardware accelerator (AES) Bit 8 ERRC: Error flag clear Upon written to 1, this bit clears the RDERR and WRERR error flags in the AES_SR register: 0: No effect 1: Clear RDERR and WRERR flags Reading the flag always returns zero. Bit 7 CCFC: Computation complete flag clear Upon written to 1, this bit clears the computation complete flag (CCF) in the AES_SR register: 0: No effect...
Page 460: Aes Status Register (Aes_Sr)
AES hardware accelerator (AES) RM0367 19.7.2 AES status register (AES_SR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 461: Aes Data Input Register (Aes_Dinr)
RM0367 AES hardware accelerator (AES) 19.7.3 AES data input register (AES_DINR) Address offset: 0x08 Reset value: 0x0000 0000 Only 32-bit access type is supported. DIN[x+31:x+16] DIN[x+15:x] Bits 31:0 This bitfield feeds a 32-bit input buffer. A 4-fold sequential write to this bitfield during the input phase DIN[x+31:x]: One of four 32-bit words of a 128-bit input data block being written into the peripheral virtually writes a complete 128-bit block of input data to the AES peripheral.
Page 462: Aes Key Register 0 (Aes_Keyr0)
AES hardware accelerator (AES) RM0367 Bits 31:0 DOUT[x+31:x]: One of four 32-bit words of a 128-bit output data block being read from the peripheral This bitfield fetches a 32-bit output buffer. A 4-fold sequential read of this bitfield, upon the computation completion (CCF set), virtually reads a complete 128-bit block of output data from the AES peripheral.
Page 463: Aes Key Register 1 (Aes_Keyr1)
RM0367 AES hardware accelerator (AES) 19.7.6 AES key register 1 (AES_KEYR1) Address offset: 0x14 Reset value: 0x0000 0000 KEY[63:48] KEY[47:32] Bits 31:0 KEY[63:32]: Cryptographic key, bits [63:32] Refer to the AES_KEYR0 register for description of the KEY[127:0] bitfield. 19.7.7 AES key register 2 (AES_KEYR2) Address offset: 0x18 Reset value: 0x0000 0000 KEY[95:80]...
Page 464: Aes Initialization Vector Register 0 (Aes_Ivr0)
AES hardware accelerator (AES) RM0367 19.7.9 AES initialization vector register 0 (AES_IVR0) Address offset: 0x20 Reset value: 0x0000 0000 IVI[31:16] IVI[15:0] Bits 31:0 IVI[31:0]: Initialization vector input, bits [31:0] Refer to Section 19.4.12: AES initialization vector registers on page 453 for description of the IVI[127:0] bitfield.
Page 465: Aes Initialization Vector Register 2 (Aes_Ivr2)
RM0367 AES hardware accelerator (AES) 19.7.11 AES initialization vector register 2 (AES_IVR2) Address offset: 0x28 Reset value: 0x0000 0000 IVI[95:80] IVI[79:64] Bits 31:0 IVI[95:64]: Initialization vector input, bits [95:64] Refer to Section 19.4.12: AES initialization vector registers on page 453 for description of the IVI[127:0] bitfield.
Page 466 AES hardware accelerator (AES) RM0367 Table 94. AES register map and reset values (continued) Offset Register AES_SR 0x0004 Reset value AES_DINR DIN[x+31:x] x=96,64,32,0 0x0008 Reset value AES_DOUTR DOUT[x+31:x] 0x000 x=96,64,32,0 Reset value AES_KEYR0 KEY[31:0] 0x0010 Reset value AES_KEYR1 KEY[63:32] 0x0014 Reset value AES_KEYR2 KEY[95:64]...
Page 467: True Random Number Generator (Rng)
RM0367 True random number generator (RNG) True random number generator (RNG) 20.1 Introduction The RNG is a true random number generator that continuously provides 32-bit entropy samples, based on an analog noise source. It can be used by the application as a live entropy source to build a NIST compliant Deterministic Random Bit Generator (DRBG).
Page 468: Rng Functional Description
True random number generator (RNG) RM0367 20.3 RNG functional description 20.3.1 RNG block diagram Figure 104 shows the RNG block diagram. Figure 104. RNG block diagram True RNG Banked Registers RNG_CR control RNG_DR data interface RNG_SR status rng_it 16-bit rng_hclk AHB clock domain Fault detection Data shift reg...
Page 469: Random Number Generation
RM0367 True random number generator (RNG) 20.3.3 Random number generation The true random number generator (RNG) delivers truly random data through its AHB interface at deterministic intervals. Within its boundary the RNG implements the entropy source model pictured on Figure 105, and provides three main functions to the application: •...
Page 470: Noise Source
True random number generator (RNG) RM0367 Noise source The noise source is the component that contains the non-deterministic, entropy-providing activity that is ultimately responsible for the uncertainty associated with the bitstring output by the entropy source. It is composed of: •...
Page 471: Health Checks
RM0367 True random number generator (RNG) Health checks This component ensures that the entire entropy source (with its noise source) starts then operates as expected, obtaining assurance that failures are caught quickly and with a high probability and reliability. The RNG implements the following health check features. Continuous health tests, running indefinitely on the output of the noise source –...
Page 472: Low-Power Operations
True random number generator (RNG) RM0367 To run the RNG in polling mode following steps are recommended: Enable the random number generation by setting the RNGEN bit to “1” in the RNG_CR register. Read the RNG_SR register and check that: –...
Page 473: Noise Source Error Detection
RM0367 True random number generator (RNG) Noise source error detection When a noise source (or seed) error occurs, the RNG stops generating random numbers and sets to “1” both SEIS and SECS bits to indicate that a seed error occurred. If a value is available in the RNG_DR register, it must not be used as it may not have enough entropy.
Page 474: Rng Entropy Source Validation
True random number generator (RNG) RM0367 20.6 RNG entropy source validation 20.6.1 Introduction In order to assess the amount of entropy available from the RNG, STMicroelectronics has tested the peripheral using NIST SP800-22 rev1a statistical tests. The results can be provided on demand or the customer can reproduce the tests.
Page 475: Rng Registers
RM0367 True random number generator (RNG) 20.7 RNG registers The RNG is associated with a control register, a data register and a status register. 20.7.1 RNG control register (RNG_CR) Address offset: 0x000 Reset value: 0x0000 0000 Res. Res. Res. Res. Res.
Page 476: Rng Status Register (Rng_Sr)
True random number generator (RNG) RM0367 20.7.2 RNG status register (RNG_SR) Address offset: 0x004 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 477: Rng Data Register (Rng_Dr)
RM0367 True random number generator (RNG) 20.7.3 RNG data register (RNG_DR) Address offset: 0x008 Reset value: 0x0000 0000 The RNG_DR register is a read-only register that delivers a 32-bit random value when read. After being read this register delivers a new random value after 42 periods of RNG clock if the output FIFO is empty.
Page 478: Rng Register Map
True random number generator (RNG) RM0367 20.7.4 RNG register map Table 97 gives the RNG register map and reset values. Table 97. RNG register map and reset map Offset Register name RNG_CR 0x000 Reset value RNG_SR 0x004 Reset value 0 0 0 RNG_DR RNDATA[31:0] 0x008...
Page 479: General-Purpose Timers (Tim2/Tim3)
RM0367 General-purpose timers (TIM2/TIM3) General-purpose timers (TIM2/TIM3) 21.1 TIM2/TIM3 introduction The general-purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM).
Page 480: Figure 106. General-Purpose Timer Block Diagram
General-purpose timers (TIM2/TIM3) RM0367 Figure 106. General-purpose timer block diagram Internal clock (CK_INT) TIMxCLK from RCC Trigger ETRF controller TRGO Polarity selection & edge ETRP TIMx_ETR Input filter detector & prescaler to other timers to DAC/ADC ITR0 ITR1 Slave ITR2 TRGI Reset, enable, up, count controller...
Page 481: Tim2/Tim3 Functional Description
RM0367 General-purpose timers (TIM2/TIM3) 21.3 TIM2/TIM3 functional description 21.3.1 Time-base unit The main block of the programmable timer is a 16-bit with its related auto-reload register. The counter can count up, down or both up and down but also down or both up and down. The counter clock can be divided by a prescaler.
Page 482: Figure 107. Counter Timing Diagram With Prescaler Division Change From 1 To 2
General-purpose timers (TIM2/TIM3) RM0367 Figure 107. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 108.
Page 483: Counter Modes
RM0367 General-purpose timers (TIM2/TIM3) 21.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An Update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 484: Figure 110. Counter Timing Diagram, Internal Clock Divided By 2
General-purpose timers (TIM2/TIM3) RM0367 Figure 110. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT 0035 0036 0000 0001 0002 0003 0034 Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31079V2 Figure 111. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 485: Figure 112. Counter Timing Diagram, Internal Clock Divided By N
RM0367 General-purpose timers (TIM2/TIM3) Figure 112. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31081V2 Figure 113. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT...
Page 486: Downcounting Mode
General-purpose timers (TIM2/TIM3) RM0367 Figure 114. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC Timerclock = CK_CNT Counter register F1 F2 F3 F4 F5 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register...
Page 487: Figure 115. Counter Timing Diagram, Internal Clock Divided By 1
RM0367 General-purpose timers (TIM2/TIM3) The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 115. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 01 00 34 33 32 Counter underflow (cnt_udf) Update event (UEV)
Page 488: Figure 117. Counter Timing Diagram, Internal Clock Divided By 4
General-purpose timers (TIM2/TIM3) RM0367 Figure 117. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0001 0000 0000 0001 Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31186V1 Figure 118. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register...
Page 489: Center-Aligned Mode (Up/Down Counting)
RM0367 General-purpose timers (TIM2/TIM3) Figure 119. Counter timing diagram, Update event when repetition counter is not used CK_PSC Timerclock = CK_CNT 30 2F Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31188V1 Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the...
Page 490: Figure 120. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6
General-purpose timers (TIM2/TIM3) RM0367 DMA request is sent). This is to avoid generating both update and capture interrupt when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): •...
Page 491: Figure 121. Counter Timing Diagram, Internal Clock Divided By 2
RM0367 General-purpose timers (TIM2/TIM3) Figure 121. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT 0002 0001 0000 0001 0002 0003 0003 Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31190V1 Figure 122. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 492: Figure 123. Counter Timing Diagram, Internal Clock Divided By N
General-purpose timers (TIM2/TIM3) RM0367 Figure 123. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31192V1 Figure 124. Counter timing diagram, Update event with ARPE=1 (counter underflow) CK_PSC Timerclock = CK_CNT 05 04 03 02...
Page 493: Clock Selection
RM0367 General-purpose timers (TIM2/TIM3) Figure 125. Counter timing diagram, Update event with ARPE=1 (counter overflow) CK_PSC Timer clock = CK_CNT Counter register 31 30 2F F8 F9 FA FB FC Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR Auto-reload active...
Page 494: External Clock Source Mode 1
General-purpose timers (TIM2/TIM3) RM0367 Figure 126. Control circuit in normal mode, internal clock divided by 1 Internal clock CEN=CNT_EN CNT_INIT Counter clock = CK_CNT = CK_PSC Counter register 33 34 35 36 03 04 05 MS31085V2 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register.
Page 495: Figure 128. Control Circuit In External Clock Mode 1
RM0367 General-purpose timers (TIM2/TIM3) For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the TIMx_CCMR1 register.
Page 496: External Clock Source Mode 2
General-purpose timers (TIM2/TIM3) RM0367 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. Figure 129 gives an overview of the external trigger input block. Figure 129.
Page 497: Capture/Compare Channels
RM0367 General-purpose timers (TIM2/TIM3) Figure 130. Control circuit in external clock mode 2 CK_INT CNT_EN ETRP ETRF Counter clock = CK_INT =CK_PSC Counter register MS33111V2 21.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).
Page 498: Figure 131. Capture/Compare Channel (Example: Channel 1 Input Stage)
General-purpose timers (TIM2/TIM3) RM0367 Figure 131. Capture/compare channel (example: channel 1 input stage) TI1F_ED To the slave mode controller TI1F_Rising TI1FP1 Filter TI1F Edge TI1F_Falling downcounter detector IC1PS Divider TI2FP1 /1, /2, /4, /8 CC1P/CC1NP ICF[3:0] TIMx_CCER TIMx_CCMR1 (from slave mode controller) TI2F_Rising (from channel 2)
Page 499: Input Capture Mode
RM0367 General-purpose timers (TIM2/TIM3) Figure 133. Output stage of capture/compare channel (channel 1) TIMx_SMCR OCCS To the master OCREF_CLR mode controller ETRF ocref_clr_int CNT > CCR1 Output Output OC1REF enable mode CNT = CCR1 circuit controller CC1P CC1E TIM1_CCER TIMx_CCER OC1M[2:0] TIMx_CCMR1 MS33146V1...
Page 500 General-purpose timers (TIM2/TIM3) RM0367 detected (sampled at f frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. Select the edge of the active transition on the TI1 channel by writing the CC1P and CC1NP bits to 00 in the TIMx_CCER register (rising edge in this case). Program the input prescaler.
Page 501: Pwm Input Mode
RM0367 General-purpose timers (TIM2/TIM3) 21.3.6 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. •...
Page 502: Forced Output Mode
General-purpose timers (TIM2/TIM3) RM0367 21.3.7 Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCxREF/OCx) to its active level, one just needs to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register.
Page 503: Pwm Mode
RM0367 General-purpose timers (TIM2/TIM3) The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 135.
Page 504: Pwm Edge-Aligned Mode
General-purpose timers (TIM2/TIM3) RM0367 In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction of the counter). However, to comply with the OCREF_CLR functionality (OCREF can be cleared by an external event through the ETR signal until the next PWM period), the OCREF signal is asserted only: •...
Page 505: Downcounting Configuration
RM0367 General-purpose timers (TIM2/TIM3) Downcounting configuration Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to Section : Downcounting mode on page 486. In PWM mode 1, the reference signal OCxREF is low as long as TIMx_CNT>TIMx_CCRx else it becomes high.
Page 506: Figure 137. Center-Aligned Pwm Waveforms (Arr=8)
General-purpose timers (TIM2/TIM3) RM0367 Figure 137. Center-aligned PWM waveforms (ARR=8) Counter register OCxREF CCRx = 4 CMS=01 CCxIF CMS=10 CMS=11 OCxREF CCRx=7 CMS=10 or 11 CCxIF ‘1’ OCxREF CCRx=8 CMS=01 CCxIF CMS=10 CMS=11 ‘1’ OCxREF CCRx>8 CMS=01 CCxIF CMS=10 CMS=11 ‘0’...
Page 507: One-Pulse Mode
RM0367 General-purpose timers (TIM2/TIM3) 21.3.10 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 508: Particular Case: Ocx Fast Enable
General-purpose timers (TIM2/TIM3) RM0367 The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1+1).
Page 509: Encoder Interface Mode
RM0367 General-purpose timers (TIM2/TIM3) Figure 139. Clearing TIMx OCxREF (CCRx) Counter (CNT) ETRF OCxREF (OCxCE = ‘0’) OCxREF (OCxCE = ‘1’) OCxREF_CLR OCxREF_CLR becomes high still high MS33105V1 1. In case of a PWM with a 100% duty cycle (if CCRx>ARR), OCxREF is enabled again at the next counter overflow.
Page 510: Table 98. Counting Direction Versus Encoder Signals
General-purpose timers (TIM2/TIM3) RM0367 position. The count direction correspond to the rotation direction of the connected sensor. The table summarizes the possible combinations, assuming TI1 and TI2 do not switch at the same time. Table 98. Counting direction versus encoder signals Level on opposite TI1FP1 signal TI2FP2 signal...
Page 511: Timer Input Xor Function
RM0367 General-purpose timers (TIM2/TIM3) Figure 140. Example of counter operation in encoder interface mode forward jitter backward jitter forward Counter down MS33107V1 Figure 141 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=1). Figure 141.
Page 512: Timers And External Trigger Synchronization
General-purpose timers (TIM2/TIM3) RM0367 21.3.14 Timers and external trigger synchronization The TIMx Timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 513: Slave Mode: Gated Mode
RM0367 General-purpose timers (TIM2/TIM3) Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we do not need any filter, so we keep IC1F=0000).
Page 514: Slave Mode: Trigger Mode
General-purpose timers (TIM2/TIM3) RM0367 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we do not need any filter, so we keep IC2F=0000).
Page 515: Slave Mode: External Clock Mode 2 + Trigger Mode
RM0367 General-purpose timers (TIM2/TIM3) Slave mode: External Clock mode 2 + trigger mode The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock input, and another input can be selected as trigger input when operating in reset mode, gated mode or trigger mode.
Page 516: Timer Synchronization
General-purpose timers (TIM2/TIM3) RM0367 Figure 145. Control circuit in external clock mode 2 + trigger mode CEN/CNT_EN Counter clock = CK_CNT = CK_PSC Counter register MS33110V1 21.3.15 Timer synchronization The TIMx timers are linked together internally for timer synchronization or chaining. When one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of another Timer configured in Slave Mode.
Page 517: Using One Timer To Enable Another Timer
RM0367 General-purpose timers (TIM2/TIM3) For example, Timer x can be configured to act as a prescaler for Timer y. Refer to Figure 146. To do this, follow the sequence below: Configure Timer x in master mode so that it outputs a periodic trigger signal on each update event UEV.
Page 518: Figure 147. Gating Timer Y With Oc1Ref Of Timer X
General-purpose timers (TIM2/TIM3) RM0367 Figure 147. Gating timer y with OC1REF of timer x CK_INT TIMERx-OC1REF TIMERx-CNT TIMERy-CNT 3045 3046 3047 3048 TIMERy-TIF Write TIF = 0 MS33137V1 In the example in Figure 147, the Timer y counter and prescaler are not initialized before being started.
Page 519: Using One Timer To Start Another Timer
RM0367 General-purpose timers (TIM2/TIM3) Figure 148. Gating timer y with Enable of timer x CK_INT TIMERx-CEN=CNT_EN TIMERx-CNT_INIT TIMERx-CNT TIMERy-CNT TIMERy-CNT_INIT TIMERy-write CNT TIMERy-TIF Write TIF = 0 MS33138V1 Using one timer to start another timer In this example, we set the enable of Timer y with the update event of Timer x. Refer to Figure 146 for connections.
Page 520: Figure 149. Triggering Timer Y With Update Of Timer X
General-purpose timers (TIM2/TIM3) RM0367 Figure 149. Triggering timer y with update of timer x CK_INT TIMERx-UEV TIMERx-CNT TIMERy-CNT TIMERy-CEN=CNT_EN TIMERy-TIF Write TIF = 0 MS33139V1 As in the previous example, both counters can be initialized before starting counting. Figure 150 shows the behavior with the same configuration as in Figure 149 but in trigger...
Page 521: Starting 2 Timers Synchronously In Response To An External Trigger
RM0367 General-purpose timers (TIM2/TIM3) Starting 2 timers synchronously in response to an external trigger In this example, we set the enable of timer x when its TI1 input rises, and the enable of Timer y with the enable of Timer x. Refer to Figure 146 for connections.
Page 522: Debug Mode
General-purpose timers (TIM2/TIM3) RM0367 21.3.16 Debug mode ® When the microcontroller enters debug mode (Cortex -M0+ core - halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module. For more details, refer to Section 33.9.2: Debug support for timers, watchdog and I 522/1043...
Page 523: Tim2/Tim3 Registers
RM0367 General-purpose timers (TIM2/TIM3) 21.4 TIM2/TIM3 registers Refer to Section 1.2 on page 52 for a list of abbreviations used in register descriptions. The 32-bit peripheral registers have to be written by words (32 bits). All other peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
Page 524 General-purpose timers (TIM2/TIM3) RM0367 Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –...
Page 525: Timx Control Register 2 (Timx_Cr2)
RM0367 General-purpose timers (TIM2/TIM3) 21.4.2 TIMx control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. TI1S MMS[2:0] CCDS Res. Res. Res. Bits 15:8 Reserved, must be kept at reset value. Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) Bits 6:4 MMS: Master mode selection...
Page 526: Timx Slave Mode Control Register (Timx_Smcr)
General-purpose timers (TIM2/TIM3) RM0367 21.4.3 TIMx slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 ETPS[1:0] ETF[3:0] TS[2:0] Res. SMS[2:0] Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is noninverted, active at high level or rising edge 1: ETR is inverted, active at low level or falling edge Bit 14 ECE: External clock enable...
Page 527: Table 99. Tim2/Tim3 Internal Trigger Connection
RM0367 General-purpose timers (TIM2/TIM3) Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Page 528: Timx Dma/Interrupt Enable Register (Timx_Dier)
General-purpose timers (TIM2/TIM3) RM0367 21.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 Res. Res. CC4DE CC3DE CC2DE CC1DE Res. Res. CC4IE CC3IE CC2IE CC1IE Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled.
Page 529: Timx Status Register (Timx_Sr)
RM0367 General-purpose timers (TIM2/TIM3) Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 21.4.5...
Page 530 General-purpose timers (TIM2/TIM3) RM0367 Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
Page 531: Timx Event Generation Register (Timx_Egr)
RM0367 General-purpose timers (TIM2/TIM3) 21.4.6 TIMx event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC4G CC3G CC2G CC1G Bits 15:7 Reserved, must be kept at reset value. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
Page 532: Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
General-purpose timers (TIM2/TIM3) RM0367 21.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 533: Input Capture Mode
RM0367 General-purpose timers (TIM2/TIM3) Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 534 General-purpose timers (TIM2/TIM3) RM0367 Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output. 01: CC2 channel is configured as input, IC2 is mapped on TI2.
Page 535: Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
RM0367 General-purpose timers (TIM2/TIM3) 21.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. OC4CE OC4M[2:0] OC4PE OC4FE OC3CE OC3M[2:0] OC3PE OC3FE CC4S[1:0] CC3S[1:0] IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0] Output compare mode Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode Bit 11 OC4PE: Output compare 4 preload enable...
Page 536: Input Capture Mode
General-purpose timers (TIM2/TIM3) RM0367 Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3...
Page 537: Table 100. Output Control Bit For Standard Ocx Channels
RM0367 General-purpose timers (TIM2/TIM3) Bit 7 CC2NP: Capture/Compare 2 output Polarity. refer to CC1NP description Bit 6 Reserved, must be kept at reset value. Bit 5 CC2P: Capture/Compare 2 output Polarity. refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable. refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 output Polarity.
Page 538: Timx Counter (Timx_Cnt)
General-purpose timers (TIM2/TIM3) RM0367 Note: The state of the external I/O pins connected to the standard OCx channels depends on the OCx channel state and the GPIO registers. 21.4.10 TIMx counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Low counter value 21.4.11 TIMx prescaler (TIMx_PSC) Address offset: 0x28...
Page 539: Timx Capture/Compare Register 1 (Timx_Ccr1)
RM0367 General-purpose timers (TIM2/TIM3) 21.4.13 TIMx capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
Page 540: Timx Capture/Compare Register 3 (Timx_Ccr3)
General-purpose timers (TIM2/TIM3) RM0367 21.4.15 TIMx capture/compare register 3 (TIMx_CCR3) Address offset: 0x3C Reset value: 0x0000 CCR3[15:0] rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r Bits 15:0 CCR3[15:0]: Low Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
Page 541: Timx Dma Control Register (Timx_Dcr)
RM0367 General-purpose timers (TIM2/TIM3) 21.4.17 TIMx DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0] Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address).
Page 542: Example Of How To Use The Dma Burst Feature
General-purpose timers (TIM2/TIM3) RM0367 Example of how to use the DMA burst feature In this example the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers. This is done in the following steps: Configure the corresponding DMA channel as follows: –...
Page 543: Tim2 Option Register (Tim2_Or)
RM0367 General-purpose timers (TIM2/TIM3) 21.4.19 TIM2 option register (TIM2_OR) Address offset: 0x50 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI4_RMP ETR_RMP Bits 15:5 Reserved, must be kept at reset value. Bits 4:3 TI4_RMP: Internal trigger (TI4 connected to TIM2_CH4) remap This bit is set and cleared by software.
Page 544: Tim3 Option Register (Tim3_Or)
General-purpose timers (TIM2/TIM3) RM0367 21.4.20 TIM3 option register (TIM3_OR) Address offset: 0x50 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI_RMP ETR_RMP Bits 15:5 Reserved, must be kept at reset value. Bit 4 TI_RMP: Timer3 remapping on PC9 This bit is set and cleared by software.
Page 545: Timx Register Map
RM0367 General-purpose timers (TIM2/TIM3) 21.5 TIMx register map TIMx registers are mapped as described in the table below: Table 101. TIM2/3 register map and reset values Offset Register TIMx_CR1 CKD [1:0] CMS[1:0] 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value TIMx_SMCR ETF[3:0] TS[2:0]...
Page 546 General-purpose timers (TIM2/TIM3) RM0367 Table 101. TIM2/3 register map and reset values (continued) Offset Register TIMx_ARR ARR[15:0] 0x2C Reset value 0x30 Res. TIMx_CCR1 CCR1[15:0] 0x34 Reset value TIMx_CCR2 CCR2[15:0] 0x38 Reset value TIMx_CCR3 CCR3[15:0] 0x3C Reset value TIMx_CCR4 CCR4[15:0] 0x40 Reset value 0x44 Res.
Page 547: General-Purpose Timers (Tim21/22)
RM0367 General-purpose timers (TIM21/22) General-purpose timers (TIM21/22) 22.1 Introduction The TIM21/22 general-purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM).
Page 548: Figure 152. General-Purpose Timer Block Diagram (Tim21/22)
General-purpose timers (TIM21/22) RM0367 Figure 152. General-purpose timer block diagram (TIM21/22) Internal clock (CK_INT) ETRF Trigger ETRP controller Polarity selection & edge Input filter TIMx_ETR TRGO ITR0 Slave Reset, enable, up, count ITR1 controller TRGI mode TI1F_ED Encoder interface TI1FP1 TI2FP2 Auto-reload register Stop, Clear...
Page 549: Tim21/22 Functional Description
RM0367 General-purpose timers (TIM21/22) 22.3 TIM21/22 functional description 22.3.1 Timebase unit The main block of the timer is a 16-bit counter with its related auto-reload register. The counters counts up, down or both up and down but also down or both up and down. The counter clock can be divided by a prescaler.
Page 550: Figure 153. Counter Timing Diagram With Prescaler Division Change From 1 To 2
General-purpose timers (TIM21/22) RM0367 Figure 153. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 550/1043 RM0367 Rev 7...
Page 551: Counter Modes
RM0367 General-purpose timers (TIM21/22) Figure 154. Counter timing diagram with prescaler division change from 1 to 4 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31077V2 22.3.2 Counter modes...
Page 552: Figure 155. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timers (TIM21/22) RM0367 The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 155. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 34 35 36 Counter overflow Update event (UEV) Update interrupt flag...
Page 553: Figure 156. Counter Timing Diagram, Internal Clock Divided By 2
RM0367 General-purpose timers (TIM21/22) Figure 156. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT 0036 0000 0002 0003 0034 0035 0001 Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31079V2 Figure 157. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 554: Figure 158. Counter Timing Diagram, Internal Clock Divided By N
General-purpose timers (TIM21/22) RM0367 Figure 158. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31081V2 Figure 159. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT...
Page 555: Downcounting Mode
RM0367 General-purpose timers (TIM21/22) Figure 160. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC Timerclock = CK_CNT Counter register F1 F2 F3 F4 F5 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register...
Page 556: Figure 161. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timers (TIM21/22) RM0367 The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 161. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 01 00 34 33 32 Counter underflow (cnt_udf) Update event (UEV)
Page 557: Figure 163. Counter Timing Diagram, Internal Clock Divided By 4
RM0367 General-purpose timers (TIM21/22) Figure 163. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0001 0000 0000 0001 Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31186V1 Figure 164. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register...
Page 558: Center-Aligned Mode (Up/Down Counting)
General-purpose timers (TIM21/22) RM0367 Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto- reload value down to 1 and generates a counter underflow event. Then it restarts counting from 0.
Page 559: Figure 165. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6
RM0367 General-purpose timers (TIM21/22) Figure 165. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 CK_PSC Timerclock = CK_CNT 02 03 04 Counter register Counter underflow Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31189V1 1. Here, center-aligned mode 1 is used (for more details refer to Section 22.4.1: TIM21/22 control register 1 (TIMx_CR1) on page 583).
Page 560: Figure 167. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36
General-purpose timers (TIM21/22) RM0367 Figure 167. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0034 0035 0036 0035 Counter overflow Update event (UEV) Update interrupt flag (UIF) Note: Here, center_aligned mode 2 or 3 is updated with an UIF on overflow MS31191V1 1.
Page 561: Figure 169. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow)
RM0367 General-purpose timers (TIM21/22) Figure 169. Counter timing diagram, Update event with ARPE=1 (counter underflow) CK_PSC Timerclock = CK_CNT 05 04 03 02 02 03 04 05 06 07 Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR...
Page 562: Clock Selection
General-purpose timers (TIM21/22) RM0367 22.3.3 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin (TIx) • External clock mode2: external trigger input (ETR connected internally to LSE) •...
Page 563: Figure 172. Ti2 External Clock Connection Example
RM0367 General-purpose timers (TIM21/22) External clock source mode 1 This mode is selected when SMS=’111’ in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input. Figure 172. TI2 external clock connection example TIMx_SMCR TS[2:0] TI2F...
Page 564: External Clock Source Mode 2
General-purpose timers (TIM21/22) RM0367 Figure 173. Control circuit in external clock mode 1 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register Write TIF=0 MS31087V2 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR.
Page 565: Capture/Compare Channels
RM0367 General-purpose timers (TIM21/22) For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
Page 566: Figure 176. Capture/Compare Channel (Example: Channel 1 Input Stage)
General-purpose timers (TIM21/22) RM0367 Figure 176. Capture/compare channel (example: channel 1 input stage) TI1F_ED To the slave mode controller TI1F_Rising TI1FP1 Filter TI1F Edge TI1F_Falling downcounter detector IC1PS Divider TI2FP1 /1, /2, /4, /8 CC1P/CC1NP ICF[3:0] TIMx_CCER TIMx_CCMR1 (from slave mode controller) TI2F_Rising (from channel 2)
Page 567: Input Capture Mode
RM0367 General-purpose timers (TIM21/22) Figure 178. Output stage of capture/compare channel (channel 1 and 2) ETRF To the master mode controller CNT > CCR2 Output Output OCx_REF mode enable CNT = CCR2 controller circuit CCxP CCxE TIMx_CCER OCxM[2:0] TIMx_CCER TIMx_CCMR1 MSv33714V1 The capture/compare block is made of one preload register and one shadow register.
Page 568 General-purpose timers (TIM21/22) RM0367 detected (sampled at f frequency). Then write IC1F bits to ‘0011’ in the TIMx_CCMR1 register. Select the edge of the active transition on the TI1 channel by programming CC1P and CC1NP bits to ‘00’ in the TIMx_CCER register (rising edge in this case). Program the input prescaler.
Page 569: Pwm Input Mode
RM0367 General-purpose timers (TIM21/22) 22.3.6 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. •...
Page 570: Forced Output Mode
General-purpose timers (TIM21/22) RM0367 22.3.7 Forced output mode In output mode (CCxS bits = ‘00’ in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCXREF/OCx) to its active level, one just needs to write ‘101’...
Page 571: Pwm Mode
RM0367 General-purpose timers (TIM21/22) The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 180.
Page 572: Figure 181. Edge-Aligned Pwm Waveforms (Arr=8)
General-purpose timers (TIM21/22) RM0367 The timer is able to generate PWM in edge-aligned mode only since the counter is upcounting. • Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Upcounting mode on page 551.
Page 573: Pwm Center-Aligned Mode
RM0367 General-purpose timers (TIM21/22) PWM center-aligned mode Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from ‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals). The compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration.
Page 574: Hints On Using Center-Aligned Mode
General-purpose timers (TIM21/22) RM0367 Hints on using center-aligned mode • When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software.
Page 575: One-Pulse Mode
RM0367 General-purpose timers (TIM21/22) Figure 183. Clearing TIMx OCxREF (CCRx) Counter (CNT) ETRF OCxREF (OCxCE = ‘0’) OCxREF (OCxCE = ‘1’) OCxREF_CLR OCxREF_CLR becomes high still high MS33105V1 Note: In case of a PWM with a 100% duty cycle (if CCRx>ARR), then OCxREF is enabled again at the next counter overflow.
Page 576: Figure 184. Example Of One Pulse Mode
General-purpose timers (TIM21/22) RM0367 Figure 184. Example of one pulse mode OC1REF TIM1_ARR TIM1_CCR1 DELAY PULSE MS31099V1 For example one may want to generate a positive pulse on OC1 with a length of t PULSE after a delay of t as soon as a positive edge is detected on the TI2 input pin.
Page 577: Particular Case: Ocx Fast Enable
RM0367 General-purpose timers (TIM21/22) Since only 1 pulse (Single mode) is needed, a 1 must be written in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the Repetitive Mode is selected.
Page 578: Table 102. Counting Direction Versus Encoder Signals
General-purpose timers (TIM21/22) RM0367 Table 102. Counting direction versus encoder signals Level on opposite TI1FP1 signal TI2FP2 signal Active edge signal (TI1FP1 for Rising Falling Rising Falling TI2, TI2FP2 for TI1) High Down No Count No Count Counting on TI1 only Down No Count No Count...
Page 579: Tim21/22 External Trigger Synchronization
RM0367 General-purpose timers (TIM21/22) Figure 186 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=1). Figure 186. Example of encoder interface mode with TI1FP1 polarity inverted forward jitter backward jitter forward Counter down down MS33108V1...
Page 580: Slave Mode: Gated Mode
General-purpose timers (TIM21/22) RM0367 The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request can be sent if enabled (depending on the TIE bit in TIMx_DIER register).
Page 581: Slave Mode: Trigger Mode
RM0367 General-purpose timers (TIM21/22) Figure 188. Control circuit in gated mode cnt_en Counter clock = ck_cnt = ck_psc Counter register 32 33 35 36 Write TIF=0 MS31402V1 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: Configure the external trigger input circuit by programming the TIMx_SMCR register as follows:...
Page 582: Timer Synchronization (Tim21/22)
General-purpose timers (TIM21/22) RM0367 Figure 189. Control circuit in trigger mode cnt_en Counter clock = ck_cnt = ck_psc Counter register MS31403V1 22.3.14 Timer synchronization (TIM21/22) The timers are linked together internally for timer synchronization or chaining. Refer to Section 21.3.15: Timer synchronization on page 516 for details.
Page 583: Tim21/22 Registers
RM0367 General-purpose timers (TIM21/22) 22.4 TIM21/22 registers Refer to Section 1.2 on page 52 for a list of abbreviations used in register descriptions. The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 22.4.1 TIM21/22 control register 1 (TIMx_CR1) Address offset: 0x00...
Page 584 General-purpose timers (TIM21/22) RM0367 Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt if enabled: – Counter overflow – Setting the UG bit 1: Only counter overflow generates an update interrupt if enabled.
Page 585: Tim21/22 Control Register 2 (Timx_Cr2)
RM0367 General-purpose timers (TIM21/22) 22.4.2 TIM21/22 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. MMS[2:0] Res. Res. Res. Res. Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 MMS: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO).
Page 586: Tim21/22 Slave Mode Control Register (Timx_Smcr)
General-purpose timers (TIM21/22) RM0367 22.4.3 TIM21/22 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 ETPS[1:0] ETF[3:0] TS[2:0] Res. SMS[2:0] Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge.
Page 587 RM0367 General-purpose timers (TIM21/22) Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 588: Table 103. Timx Internal Trigger Connection
General-purpose timers (TIM21/22) RM0367 Bits 6:4 TS: Trigger selection This bitfield selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0) 001: Internal Trigger 1 (ITR1) 010: Reserved 011: Reserved 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) 111: Reserved.
Page 589: Tim21/22 Interrupt Enable Register (Timx_Dier)
RM0367 General-purpose timers (TIM21/22) 22.4.4 TIM21/22 Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC2IE CC1IE Bits 15:7 Reserved, must be kept at reset value. Bit 6 TIE: Trigger interrupt enable 0: Trigger interrupt disabled.
Page 590 General-purpose timers (TIM21/22) RM0367 Bit 6 TIF: Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected.
Page 591: Tim21/22 Event Generation Register (Timx_Egr)
RM0367 General-purpose timers (TIM21/22) 22.4.6 TIM21/22 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC2G CC1G Bits 15:7 Reserved, must be kept at reset value. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
Page 592: Tim21/22 Capture/Compare Mode Register 1 (Timx_Ccmr1)
General-purpose timers (TIM21/22) RM0367 22.4.7 TIM21/22 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits in this register have different functions in input and output modes.
Page 593 RM0367 General-purpose timers (TIM21/22) Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas the active levels of OC1 and OC1N depend on the CC1P and CC1NP bits, respectively.
Page 594: Input Capture Mode
General-purpose timers (TIM21/22) RM0367 Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1...
Page 595: Tim21/22 Capture/Compare Enable Register (Timx_Ccer)
RM0367 General-purpose timers (TIM21/22) 22.4.8 TIM21/22 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. CC2NP Res. CC2P CC2E CC1NP Res. CC1P CC1E Bits 15:8 Reserved, must be kept at reset value. Bit 7 CC2NP: Capture/Compare 2 output Polarity refer to CC1NP description Bit 6 Reserved, must be kept at reset value.
Page 596: Tim21/22 Counter (Timx_Cnt)
General-purpose timers (TIM21/22) RM0367 Table 104. Output control bit for standard OCx channels CCxE bit OCx output state Output disabled (OCx=’0’, OCx_EN=’0’) OCx=OCxREF + Polarity, OCx_EN=’1’ Note: The states of the external I/O pins connected to the standard OCx channels depend on the state of the OCx channel and on the GPIO registers.
Page 597: Tim21/22 Capture/Compare Register 1 (Timx_Ccr1)
RM0367 General-purpose timers (TIM21/22) 22.4.12 TIM21/22 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded into the actual capture/compare 1 register (preload value).
Page 598: Tim21 Option Register (Tim21_Or)
General-purpose timers (TIM21/22) RM0367 22.4.14 TIM21 option register (TIM21_OR) Address offset: 0x50 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI2_RMP TI1_RMP ETR_RMP Bits 15:6 Reserved, must be kept at reset value. Bit 5 TI2_RMP: Timer21 TI2 (connected to TIM21_CH1) remap This bit is set and cleared by software.
Page 599: Tim22 Option Register (Tim22_Or)
RM0367 General-purpose timers (TIM21/22) 22.4.15 TIM22 option register (TIM22_OR) Address offset: 0x50 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI1_RMP ETR_RMP Bits 15:4 Reserved, must be kept at reset value. Bits 3:2 TI1_RMP: Timer 22 TI1 (connected to TIM22_CH1) remap This bit is set and cleared by software.
Page 600: Tim21/22 Register Map
General-purpose timers (TIM21/22) RM0367 22.4.16 TIM21/22 register map The table below shows TIM21/22 register map and reset values. Table 105. TIM21/22 register map and reset values Offset Register TIMx_CR1 [1:0] [1:0] 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value TIMx_SMCR ETF[3:0] TS[2:0] SMS[2:0]...
Page 601 RM0367 General-purpose timers (TIM21/22) Table 105. TIM21/22 register map and reset values (continued) Offset Register TIMx_PSC PSC[15:0] 0x28 Reset value TIMx_ARR ARR[15:0] 0x2C Reset value 0x30 Res. TIMx_CCR1 CCR1[15:0] 0x34 Reset value TIMx_CCR2 CCR2[15:0] 0x38 Reset value 0x3C to Res. 0x4C TIMx_CCR2 CCR2[15:0]...
Page 602: Basic Timers (Tim6/7)
Basic timers (TIM6/7) RM0367 Basic timers (TIM6/7) 23.1 Introduction The basic timers TIM6, TIM7 consist of a 16-bit auto-reload counter driven by a programmable prescaler. They can be used as generic timers for timebase generation but they are also specifically used to drive the digital-to-analog converter (DAC).
Page 603: Tim6/7 Functional Description
RM0367 Basic timers (TIM6/7) 23.3 TIM6/7 functional description 23.3.1 Time-base unit The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 604: Figure 191. Counter Timing Diagram With Prescaler Division Change From 1 To 2
Basic timers (TIM6/7) RM0367 Figure 191. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 192.
Page 605: Counting Mode
RM0367 Basic timers (TIM6/7) 23.3.2 Counting mode The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An update event can be generate at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 606: Figure 194. Counter Timing Diagram, Internal Clock Divided By 2
Basic timers (TIM6/7) RM0367 Figure 194. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT 0035 0036 0000 0001 0002 0003 0034 Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31079V2 Figure 195. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 607: Figure 196. Counter Timing Diagram, Internal Clock Divided By N
RM0367 Basic timers (TIM6/7) Figure 196. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31081V2 Figure 197. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT...
Page 608: Clock Source
Basic timers (TIM6/7) RM0367 Figure 198. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC Timerclock = CK_CNT Counter register F1 F2 F3 F4 F5 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register...
Page 609: Debug Mode
RM0367 Basic timers (TIM6/7) Figure 199. Control circuit in normal mode, internal clock divided by 1 Internal clock CEN=CNT_EN CNT_INIT Counter clock = CK_CNT = CK_PSC Counter register 33 34 35 36 03 04 05 MS31085V2 23.3.4 Debug mode ® When the microcontroller enters the debug mode (Cortex -M0+ core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP...
Page 610: Tim6/7 Registers
Basic timers (TIM6/7) RM0367 23.4 TIM6/7 registers Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in register descriptions. The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
Page 611: Tim6/7 Control Register 2 (Timx_Cr2)
RM0367 Basic timers (TIM6/7) 23.4.2 TIM6/7 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. MMS[2:0] Res. Res. Res. Res. Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 MMS: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO).
Page 612: Tim6/7 Status Register (Timx_Sr)
Basic timers (TIM6/7) RM0367 23.4.4 TIM6/7 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rc_w0 Bits 15:1 Reserved, must be kept at reset value. Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event.
Page 613: Tim6/7 Prescaler (Timx_Psc)
RM0367 Basic timers (TIM6/7) 23.4.7 TIM6/7 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to f / (PSC[15:0] + 1). CK_PSC PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).
Page 614: Tim6/7 Register Map
Basic timers (TIM6/7) RM0367 23.4.9 TIM6/7 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 106. TIM6/7 register map and reset values Offset Register TIMx_CR1 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value 0x08 Res.
Page 615: Low-Power Timer (Lptim)
RM0367 Low-power timer (LPTIM) Low-power timer (LPTIM) 24.1 Introduction The LPTIM is a 16-bit timer that benefits from the ultimate developments in power consumption reduction. Thanks to its diversity of clock sources, the LPTIM is able to keep running in all power modes except for Standby mode. Given its capability to run even with no internal clock source, the LPTIM can be used as a “Pulse Counter”...
Page 616: Lptim Implementation
Low-power timer (LPTIM) RM0367 24.3 LPTIM implementation Table 107 describes LPTIM implementation on STM32L0x3 devices. Table 107. STM32L0x3 LPTIM features LPTIM modes/features LPTIM1 Encoder mode 1. X = supported. 24.4 LPTIM functional description 24.4.1 LPTIM block diagram Figure 200. Low-power timer block diagram...
Page 617: Lptim Trigger Mapping
RM0367 Low-power timer (LPTIM) 24.4.2 LPTIM trigger mapping The LPTIM external trigger connections are detailed hereafter: Table 108. LPTIM1 external trigger connection TRIGSEL External trigger lptim_ext_trig0 PB6 or PC3 lptim_ext_trig1 RTC alarm A lptim_ext_trig2 RTC alarm B lptim_ext_trig3 RTC_TAMP1 input detection lptim_ext_trig4 RTC_TAMP2 input detection lptim_ext_trig5...
Page 618: Prescaler
Low-power timer (LPTIM) RM0367 The digital filters are divided into two groups: • The first group of digital filters protects the LPTIM external inputs. The digital filters sensitivity is controlled by the CKFLT bits • The second group of digital filters protects the LPTIM internal trigger inputs. The digital filters sensitivity is controlled by the TRGFLT bits.
Page 619: Trigger Multiplexer
RM0367 Low-power timer (LPTIM) 24.4.6 Trigger multiplexer The LPTIM counter may be started either by software or after the detection of an active edge on one of the 8 trigger inputs. TRIGEN[1:0] is used to determine the LPTIM trigger source: •...
Page 620: Continous Mode
Low-power timer (LPTIM) RM0367 Figure 202. LPTIM output waveform, single counting mode configuration LPTIM_ARR Compare External trigger event MSv39230V2 - Set-once mode activated: It should be noted that when the WAVE bit-field in the LPTIM_CFGR register is set, the Set- once mode is activated.
Page 621: Timeout Function
RM0367 Low-power timer (LPTIM) Figure 204. LPTIM output waveform, Continuous counting mode configuration Discarded triggers LPTIM_ARR Compare External trigger event MSv39229V2 SNGSTRT and CNTSTRT bits can only be set when the timer is enabled (The ENABLE bit is set to ‘1’). It is possible to change “on the fly” from One-shot mode to Continuous mode. If the Continuous mode was previously selected, setting SNGSTRT will switch the LPTIM to the One-shot mode.
Page 622: Register Update
Low-power timer (LPTIM) RM0367 The LPTIM output waveform can be configured through the WAVE bit as follow: • Resetting the WAVE bit to ‘0’ forces the LPTIM to generate either a PWM waveform or a One pulse waveform depending on which bit is set: CNTSTRT or SNGSTRT. •...
Page 623: Counter Mode
RM0367 Low-power timer (LPTIM) counter comparator. Within this latency period, any additional write into these registers must be avoided. The ARROK flag and the CMPOK flag in the LPTIM_ISR register indicate when the write operation is completed to respectively the LPTIM_ARR register and the LPTIM_CMP register.
Page 624: Timer Enable
Low-power timer (LPTIM) RM0367 24.4.12 Timer enable The ENABLE bit located in the LPTIM_CR register is used to enable/disable the LPTIM kernel logic. After setting the ENABLE bit, a delay of two counter clock is needed before the LPTIM is actually enabled. The LPTIM_CFGR and LPTIM_IER registers must be modified only when the LPTIM is disabled.
Page 625: Debug Mode
RM0367 Low-power timer (LPTIM) The following figure shows a counting sequence for Encoder mode where both-edge sensitivity is configured. Caution: In this mode the LPTIM must be clocked by an internal clock source, so the CKSEL bit must be maintained to its reset value which is equal to ‘0’. Also, the prescaler division ratio must be equal to its reset value which is 1 (PRESC[2:0] bits must be ‘000’).
Page 626: Lptim Interrupts
Low-power timer (LPTIM) RM0367 24.6 LPTIM interrupts The following events generate an interrupt/wake-up event, if they are enabled through the LPTIM_IER register: • Compare match • Auto-reload match (whatever the direction if encoder mode) • External trigger event • Autoreload register write completed •...
Page 627: Lptim Interrupt And Status Register (Lptim_Isr)
RM0367 Low-power timer (LPTIM) 24.7.1 LPTIM interrupt and status register (LPTIM_ISR) Address offset: 0x000 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 628: Lptim Interrupt Clear Register (Lptim_Icr)
Low-power timer (LPTIM) RM0367 24.7.2 LPTIM interrupt clear register (LPTIM_ICR) Address offset: 0x004 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWN ARRO CMPO EXTTR ARRM CMPM Res. Res.
Page 629: Lptim Configuration Register (Lptim_Cfgr)
RM0367 Low-power timer (LPTIM) Bits 31:7 Reserved, must be kept at reset value. Bit 6 DOWNIE: Direction change to down Interrupt Enable DOWN interrupt disabled DOWN interrupt enabled Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to Section 24.3: LPTIM implementation.
Page 630 Low-power timer (LPTIM) RM0367 Bit 24 ENC: Encoder mode enable The ENC bit controls the Encoder mode 0: Encoder mode disabled 1: Encoder mode enabled Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to Section 24.3: LPTIM implementation.
Page 631 RM0367 Low-power timer (LPTIM) Bits 15:13 TRIGSEL[2:0]: Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: 000: lptim_ext_trig0 001: lptim_ext_trig1 010: lptim_ext_trig2 011: lptim_ext_trig3 100: lptim_ext_trig4 101: lptim_ext_trig5 110: lptim_ext_trig6...
Page 632: Lptim Control Register (Lptim_Cr)
Low-power timer (LPTIM) RM0367 Bits 4:3 CKFLT[1:0]: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any external clock signal level change is considered as a valid transition 01: external clock signal level change must be stable for at least 2 clock periods before it is...
Page 633: Lptim Compare Register (Lptim_Cmp)
RM0367 Low-power timer (LPTIM) Bits 31:3 Reserved, must be kept at reset value. Bit 2 CNTSTRT: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected.
Page 634: Lptim Autoreload Register (Lptim_Arr)
Low-power timer (LPTIM) RM0367 24.7.7 LPTIM autoreload register (LPTIM_ARR) Address offset: 0x018 Reset value: 0x0000 0001 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ARR[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 ARR[15:0]: Auto reload value ARR is the autoreload value for the LPTIM.
Page 635: Lptim Register Map
RM0367 Low-power timer (LPTIM) 24.7.9 LPTIM register map The following table summarizes the LPTIM registers. Table 113. LPTIM register map and reset values Offset Register name LPTIM_ISR 0x000 0 0 0 0 0 0 0 Reset value LPTIM_ICR 0x004 0 0 0 0 0 0 0 Reset value LPTIM_IER 0x008...
Page 636: Independent Watchdog (Iwdg)
Independent watchdog (IWDG) RM0367 Independent watchdog (IWDG) 25.1 Introduction The devices feature an embedded watchdog peripheral that offers a combination of high safety level, timing accuracy and flexibility of use. The Independent watchdog peripheral detects and solves malfunctions due to software failure, and triggers system reset when the counter reaches a given timeout value.
Page 637: Window Option
RM0367 Independent watchdog (IWDG) When the independent watchdog is started by writing the value 0x0000 CCCC in the IWDG key register (IWDG_KR), the counter starts counting down from the reset value of 0xFFF. When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset). Whenever the key value 0x0000 AAAA is written in the IWDG key register (IWDG_KR), the...
Page 638: Hardware Watchdog
Independent watchdog (IWDG) RM0367 25.3.3 Hardware watchdog If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and generates a reset unless the IWDG key register (IWDG_KR) is written by the software before the counter reaches end of count or if the downcounter is reloaded inside the window.
Page 639: Iwdg Registers
RM0367 Independent watchdog (IWDG) 25.4 IWDG registers Refer to Section 1.2 on page 52 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 25.4.1 IWDG key register (IWDG_KR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by Standby mode) Res.
Page 640: Iwdg Prescaler Register (Iwdg_Pr)
Independent watchdog (IWDG) RM0367 25.4.2 IWDG prescaler register (IWDG_PR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 641: Iwdg Reload Register (Iwdg_Rlr)
RM0367 Independent watchdog (IWDG) 25.4.3 IWDG reload register (IWDG_RLR) Address offset: 0x08 Reset value: 0x0000 0FFF (reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RL[11:0] Bits 31:12 Reserved, must be kept at reset value.
Page 642: Iwdg Status Register (Iwdg_Sr)
Independent watchdog (IWDG) RM0367 25.4.4 IWDG status register (IWDG_SR) Address offset: 0x0C Reset value: 0x0000 0000 (not reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 643: Iwdg Window Register (Iwdg_Winr)
RM0367 Independent watchdog (IWDG) 25.4.5 IWDG window register (IWDG_WINR) Address offset: 0x10 Reset value: 0x0000 0FFF (reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WIN[11:0] Bits 31:12 Reserved, must be kept at reset value.
Page 644: Iwdg Register Map
Independent watchdog (IWDG) RM0367 25.4.6 IWDG register map The following table gives the IWDG register map and reset values. Table 114. IWDG register map and reset values Register Offset name IWDG_KR KEY[15:0] 0x00 Reset value IWDG_PR PR[2:0] 0x04 Reset value IWDG_RLR RL[11:0] 0x08...
Page 645: System Window Watchdog (Wwdg)
RM0367 System window watchdog (WWDG) System window watchdog (WWDG) 26.1 Introduction The system window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the down-counter before the T6 bit becomes cleared.
Page 646: Wwdg Block Diagram
System window watchdog (WWDG) RM0367 26.3.1 WWDG block diagram Figure 208. Watchdog block diagram WWDG Register interface CMP = 1 when T[6:0] > W[6:0] W[6:0] WWDG_CFR wwdg_out_rst WWDG_SR WDGA Write to WWDG_CR T[6:0] readback WWDG_CR T[6:0] wwdg_it EWIF cnt_out preload 7-bit DownCounter (CNT) WDGTB pclk...
Page 647: Figure 209. Window Watchdog Timing Diagram
RM0367 System window watchdog (WWDG) Figure 209. Window watchdog timing diagram CNT DownCounter Refresh not allowed Refresh allowed T[6:0] W[6:0] 0x3F Time WDGTB x 4096 x 2 pclk 0x41 0x40 0x3F wwdg_ewit EWIF = 0 wwdg_rst T6 bit MS47266V1 The formula to calculate the timeout value is given by: WDGTB[1:0] ×...
Page 648: Debug Mode
System window watchdog (WWDG) RM0367 26.3.5 Debug mode When the device enters debug mode (processor halted), the WWDG counter either continues to work normally or stops, depending on the configuration bit in DBG module. For more details refer to Section 33.9.2: Debug support for timers, watchdog and I 26.4 WWDG interrupts The early wakeup interrupt (EWI) can be used if specific safety operations or data logging...
Page 649: Wwdg Configuration Register (Wwdg_Cfr)
RM0367 System window watchdog (WWDG) Bits 31:8 Reserved, must be kept at reset value. Bit 7 WDGA: Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB)
Page 650: Wwdg Register Map
System window watchdog (WWDG) RM0367 Bits 31:1 Reserved, must be kept at reset value. Bit 0 EWIF: Early wakeup interrupt flag This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing ‘0’. Writing ‘1’ has no effect. This bit is also set if the interrupt is not enabled.
Page 651: Real-Time Clock (Rtc)
RM0367 Real-time clock (RTC) Real-time clock (RTC) 27.1 Introduction The RTC provides an automatic wakeup to manage all low-power modes. The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time- of-day clock/calendar with programmable alarm interrupts. The RTC includes also a periodic programmable wakeup flag with interrupt capability.
Page 652: Rtc Main Features
Real-time clock (RTC) RM0367 27.2 RTC main features The RTC unit main features are the following (see Figure 210: RTC block diagram): • Calendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of week), date (day of month), month, and year. •...
Page 653: Rtc Functional Description
RM0367 Real-time clock (RTC) 27.4 RTC functional description 27.4.1 RTC block diagram Figure 210. RTC block diagram RTC_TAMP2 Backup registers RTC_TAMP1 TAMPxF and RTC tamper control registers RTC_TAMP3 RTC_TS Time stamp registers RTC_REFIN LSE (32.768 Hz) prescaled RTCCLK ck_spre RTC_CALR RTC_PRER RTC_PRER ck_apre...
Page 654: Table 117. Rtc Pin Pc13 Configuration
Real-time clock (RTC) RM0367 The RTC includes: • Two alarms • Up to three tamper events from I/Os – Tamper detection erases the backup registers. • One timestamp event from I/O • Tamper event detection can generate a timestamp event •...
Page 655: Table 118. Rtc_Out Mapping
RM0367 Real-time clock (RTC) Table 117. RTC pin PC13 configuration (continued) OSEL[1:0] TSE bit COE bit TAMP1E bit bits RTC_OUT PC13 Pin RTC_ALARM (RTC_CALIB (RTC_TAMP1 (RTC_TS configuration _TYPE (RTC_ALARM _RMP output input input and function output enable) enable) enable) enable) Don’t care RTC_TS and RTC_TAMP1...
Page 656 Real-time clock (RTC) RM0367 A programmable prescaler stage generates a 1 Hz clock which is used to update the calendar. To minimize power consumption, the prescaler is split into 2 programmable prescalers (see Figure 210: RTC block diagram): • A 7-bit asynchronous prescaler configured through the PREDIV_A bits of the RTC_PRER register.
Page 657 RM0367 Real-time clock (RTC) BYPSHAD control bit in the RTC_CR register. By default, this bit is cleared, and the user accesses the shadow registers. When reading the RTC_SSR, RTC_TR or RTC_DR registers in BYPSHAD=0 mode, the frequency of the APB clock (f ) must be at least 7 times the frequency of the RTC clock RTCCLK The shadow registers are reset by system reset.
Page 658 Real-time clock (RTC) RM0367 When the periodic wakeup interrupt is enabled by setting the WUTIE bit in the RTC_CR register, it can exit the device from low-power modes. The periodic wakeup flag can be routed to the RTC_ALARM output provided it has been enabled through bits OSEL[1:0] of RTC_CR register.
Page 659 RM0367 Real-time clock (RTC) Note: After a system reset, the application can read the INITS flag in the RTC_ISR register to check if the calendar has been initialized or not. If this flag equals 0, the calendar has not been initialized since the year field is set at its RTC domain reset default value (0x00). To read the calendar after initialization, the software must first check that the RSF flag is set in the RTC_ISR register.
Page 660 Real-time clock (RTC) RM0367 If the APB1 clock frequency is less than seven times the RTC clock frequency, the software must read the calendar time and date registers twice. If the second read of the RTC_TR gives the same result as the first read, this ensures that the data is correct. Otherwise a third read access must be done.
Page 661 RM0367 Real-time clock (RTC) On the contrary, the following registers are reset to their default values by a RTC domain reset and are not affected by a system reset: the RTC current calendar registers, the RTC control register (RTC_CR), the prescaler register (RTC_PRER), the RTC calibration register (RTC_CALR), the RTC shift register (RTC_SHIFTR), the RTC timestamp registers (RTC_TSSSR, RTC_TSTR and RTC_TSDR), the RTC tamper configuration register (RTC_TAMPCR), the RTC backup registers (RTC_BKPxR), the wakeup timer register...
Page 662 Real-time clock (RTC) RM0367 detection is enabled (REFCKON bit of RTC_CR set to 1), the calendar is still clocked by the LSE, and RTC_REFIN is used to compensate for the imprecision of the calendar update frequency (1 Hz). Each 1 Hz clock edge is compared to the nearest RTC_REFIN clock edge (if one is found within a given time window).
Page 663 RM0367 Real-time clock (RTC) Note: CALM[8:0] (RTC_CALR) specifies the number of RTCCLK pulses to be masked during the 32-second cycle. Setting the bit CALM[0] to ‘1’ causes exactly one pulse to be masked during the 32-second cycle at the moment when cal_cnt[19:0] is 0x80000; CALM[1]=1 causes two other cycles to be masked (when cal_cnt is 0x40000 and 0xC0000);...
Page 664 Real-time clock (RTC) RM0367 However, this measurement error can be eliminated if the measurement period is the same length as the calibration cycle period. In this case, the only error observed is the error due to the resolution of the digital calibration. •...
Page 665 RM0367 Real-time clock (RTC) Note: TSF is set 2 ck_apre cycles after the time-stamp event occurs due to synchronization process. There is no delay in the setting of TSOVF. This means that if two time-stamp events are close together, TSOVF can be seen as '1' while TSF is still '0'. As a consequence, it is recommended to poll TSOVF only after TSF has been set.
Page 666 Real-time clock (RTC) RM0367 A new tamper occurring on the same pin cannot be detected during the latency described above and 2.5 ck_rtc additional cycles. By setting the TAMPIE bit in the RTC_TAMPCR register, an interrupt is generated when a tamper detection event occurs (when TAMPxF is set).
Page 667 RM0367 Real-time clock (RTC) The RTC_TAMPx inputs are precharged through the I/O internal pull-up resistance before its state is sampled, unless disabled by setting TAMPPUDIS to 1,The duration of the precharge is determined by the TAMPPRCH bits, allowing for larger capacitances on the RTC_TAMPx inputs.
Page 668: Table 119. Effect Of Low-Power Modes On Rtc
Real-time clock (RTC) RM0367 27.5 RTC low-power modes Table 119. Effect of low-power modes on RTC Mode Description No effect Sleep RTC interrupts cause the device to exit the Sleep mode. The RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC Stop tamper event, RTC timestamp event, and RTC Wakeup cause the device to exit the Stop mode.
Page 669 Bits 14:12 MNT[2:0]: Minute tens in BCD format Bits 11:8 MNU[3:0]: Minute units in BCD format Bit 7 Reserved, must be kept at reset value. Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format RM0367 Rev 7...
Page 670 Real-time clock (RTC) RM0367 27.7.2 RTC date register (RTC_DR) The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page 658 Reading the calendar on page 659.
Page 671: Rtc Control Register (Rtc_Cr)
RM0367 Real-time clock (RTC) 27.7.3 RTC control register (RTC_CR) Address offset: 0x08 RTC domain reset value: 0x0000 0000 System reset: not affected Res. Res. Res. Res. Res. Res. Res. Res. OSEL[1:0] COSEL SUB1H ADD1H BYPS TSIE WUTIE ALRBIE ALRAIE WUTE ALRBE ALRAE Res.
Page 672 Real-time clock (RTC) RM0367 Bit 16 ADD1H: Add 1 hour (summer time change) When this bit is set, 1 hour is added to the calendar time. This bit is always read as 0. 0: No effect 1: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode.
Page 673 RM0367 Real-time clock (RTC) Bit 4 REFCKON: RTC_REFIN reference clock detection enable (50 or 60 Hz) 0: RTC_REFIN detection disabled 1: RTC_REFIN detection enabled Note: PREDIV_S must be 0x00FF. Bit 3 TSEDGE: Time-stamp event active edge 0: RTC_TS input rising edge generates a time-stamp event 1: RTC_TS input falling edge generates a time-stamp event TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.
Page 674: Rtc Initialization And Status Register (Rtc_Isr)
Real-time clock (RTC) RM0367 27.7.4 RTC initialization and status register (RTC_ISR) This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure is described in RTC register write protection on page 658. Address offset: 0x0C RTC domain reset value: 0x0000 0007 System reset: not affected except INIT, INITF, and RSF bits which are cleared to ‘0’...
Page 675 RM0367 Real-time clock (RTC) Bit 9 ALRBF: Alarm B flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR). This flag is cleared by software by writing 0. Bit 8 ALRAF: Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR).
Page 676 Real-time clock (RTC) RM0367 Bit 2 WUTWF: Wakeup timer write flag This bit is set by hardware up to 2 RTCCLK cycles after the WUTE bit has been set to 0 in RTC_CR, and is cleared up to 2 RTCCLK cycles after the WUTE bit has been set to 1. The wakeup timer values can be changed when WUTE bit is cleared and WUTWF is set.
Page 677: Rtc Prescaler Register (Rtc_Prer)
RM0367 Real-time clock (RTC) 27.7.5 RTC prescaler register (RTC_PRER) This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page 658. This register is write protected. The write access procedure is described in RTC register write protection on page 658.
Page 678: Rtc Wakeup Timer Register (Rtc_Wutr)
Real-time clock (RTC) RM0367 27.7.6 RTC wakeup timer register (RTC_WUTR) This register can be written only when WUTWF is set to 1 in RTC_ISR. This register is write protected. The write access procedure is described in RTC register write protection on page 658.
Page 679: Rtc Alarm A Register (Rtc_Alrmar)
Bit 7 MSK1: Alarm A seconds mask 0: Alarm A set if the seconds match 1: Seconds don’t care in Alarm A comparison Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. RM0367 Rev 7...
Page 680: Rtc Alarm B Register (Rtc_Alrmbr)
Bit 7 MSK1: Alarm B seconds mask 0: Alarm B set if the seconds match 1: Seconds don’t care in Alarm B comparison Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format 680/1043...
Page 681: Rtc Write Protection Register (Rtc_Wpr)
RM0367 Real-time clock (RTC) 27.7.9 RTC write protection register (RTC_WPR) Address offset: 0x24 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 682: Rtc Shift Control Register (Rtc_Shiftr)
Real-time clock (RTC) RM0367 27.7.11 RTC shift control register (RTC_SHIFTR) This register is write protected. The write access procedure is described in RTC register write protection on page 658. Address offset: 0x2C RTC domain reset value: 0x0000 0000 System reset: not affected ADD1S Res.
Page 683: Rtc Timestamp Time Register (Rtc_Tstr)
Bits 14:12 MNT[2:0]: Minute tens in BCD format. Bits 11:8 MNU[3:0]: Minute units in BCD format. Bit 7 Reserved, must be kept at reset value. Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. RM0367 Rev 7...
Page 684: Rtc Timestamp Date Register (Rtc_Tsdr)
Real-time clock (RTC) RM0367 27.7.13 RTC timestamp date register (RTC_TSDR) The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset. Address offset: 0x34 RTC domain reset value: 0x0000 0000 System reset: not affected Res.
Page 685: Rtc Time-Stamp Sub Second Register (Rtc_Tsssr)
RM0367 Real-time clock (RTC) 27.7.14 RTC time-stamp sub second register (RTC_TSSSR) The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the RTC_ISR/TSF bit is reset. Address offset: 0x38 RTC domain reset value: 0x0000 0000 System reset: not affected Res.
Page 686: Rtc Calibration Register (Rtc_Calr)
Real-time clock (RTC) RM0367 27.7.15 RTC calibration register (RTC_CALR) This register is write protected. The write access procedure is described in RTC register write protection on page 658. Address offset: 0x3C RTC domain reset value: 0x0000 0000 System reset: not affected Res.
Page 687: Rtc Tamper Configuration Register (Rtc_Tampcr)
RM0367 Real-time clock (RTC) 27.7.16 RTC tamper configuration register (RTC_TAMPCR) Address offset: 0x40 RTC domain reset value: 0x0000 0000 System reset: not affected TAMP3 TAMP2 TAMP1 TAMP3 TAMP3 TAMP2 TAMP2 TAMP1 TAMP1 Res. Res. Res. Res. Res. Res. Res. ERASE ERASE ERASE TAMP...
Page 688 Real-time clock (RTC) RM0367 Bit 17 TAMP1NOERASE: Tamper 1 no erase 0: Tamper 1 event erases the backup registers. 1: Tamper 1 event does not erase the backup registers. Bit 16 TAMP1IE: Tamper 1 interrupt enable 0: Tamper 1 interrupt is disabled if TAMPIE = 0. 1: Tamper 1 interrupt enabled.
Page 689 RM0367 Real-time clock (RTC) Bit 5 TAMP3E: RTC_TAMP3 detection enable 0: RTC_TAMP3 input detection disabled 1: RTC_TAMP3 input detection enabled Bit 4 TAMP2TRG: Active level for RTC_TAMP2 input if TAMPFLT != 00: 0: RTC_TAMP2 input staying low triggers a tamper detection event. 1: RTC_TAMP2 input staying high triggers a tamper detection event.
Page 690: Rtc Alarm A Sub Second Register (Rtc_Alrmassr)
Real-time clock (RTC) RM0367 27.7.17 RTC alarm A sub second register (RTC_ALRMASSR) This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page 658 Address offset: 0x44...
Page 691: Rtc Alarm B Sub Second Register (Rtc_Alrmbssr)
RM0367 Real-time clock (RTC) 27.7.18 RTC alarm B sub second register (RTC_ALRMBSSR) This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode. This register is write protected.The write access procedure is described in Section : RTC register write protection.
Page 692: Rtc Option Register (Rtc_Or)
Real-time clock (RTC) RM0367 27.7.19 RTC option register (RTC_OR) Address offset: 0x4C RTC domain reset value: 0x0000 0000 System reset: not affected Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RTC_ RTC_ Res.
Page 693: Rtc Register Map
RM0367 Real-time clock (RTC) 27.7.21 RTC register map Table 121. RTC register map and reset values Register Offset name RTC_TR HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] 0x00 Reset value RTC_DR YT[3:0] YU[3:0] WDU[2:0] MU[3:0] DU[3:0] 0x04 Reset value RTC_CR 0x08 Reset value...
Page 694 Real-time clock (RTC) RM0367 Table 121. RTC register map and reset values (continued) Register Offset name RTC_TSDR WDU[1:0] MU[3:0] DU[3:0] 0x34 Reset value RTC_TSSSR SS[15:0] 0x38 Reset value RTC_ CALR CALM[8:0] 0x3C Reset value RTC_TAMPCR 0x40 Reset value RTC_ MASKSS SS[14:0] ALRMASSR [3:0]...
Page 695: Inter-Integrated Circuit (I2C) Interface
RM0367 Inter-integrated circuit (I2C) interface Inter-integrated circuit (I2C) interface 28.1 Introduction The I C (inter-integrated circuit) bus interface handles communications between the microcontroller and the serial I C bus. It provides multimaster capability, and controls all I bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+).
Page 696: I2C Implementation
I2C implementation This manual describes the full set of features implemented in I2C1, I2C3. I2C2 supports a smaller set of features, but is otherwise identical to I2C1/I2C3. The differences are listed below. Table 122. STM32L0x3 I2C features I2C features I2C1 I2C2...
Page 697: I2C1/3 Block Diagram
RM0367 Inter-integrated circuit (I2C) interface If SMBus feature is supported: the additional optional SMBus Alert pin (SMBA) is also available. 28.4.1 I2C1/3 block diagram The block diagram of the I2C1 interface is shown in Figure 211. Figure 211. I2C1/3 block diagram I2CCLK i2c_ker_ck Data control...
Page 698: I2C2 Block Diagram
Inter-integrated circuit (I2C) interface RM0367 28.4.2 I2C2 block diagram The block diagram of the I2C2 interface is shown in Figure 212. Figure 212. I2C2 block diagram I2CCLK PCLK Data control Digital Analog Shift register noise noise GPIO I2C1_SDA filter filter logic SMBUS generation/...
Page 699: I2C Pins And Internal Signals
RM0367 Inter-integrated circuit (I2C) interface 28.4.3 I2C pins and internal signals Table 123. I2C input/output pins Pin name Signal type Description I2C_SDA Bidirectional I2C data I2C_SCL Bidirectional I2C clock I2C_SMBA Bidirectional SMBus alert Table 124. I2C internal input/output signals Internal signal name Signal type Description I2C kernel clock, also named I2CCLK in this...
Page 700: Communication Flow
Inter-integrated circuit (I2C) interface RM0367 By default, it operates in slave mode. The interface automatically switches from slave to master when it generates a START condition, and from master to slave if an arbitration loss or a STOP generation occurs, allowing multimaster capability. Communication flow In Master mode, the I2C interface initiates a data transfer and generates the clock signal.
Page 701: Table 125. Comparison Of Analog Vs. Digital Filters
RM0367 Inter-integrated circuit (I2C) interface suppression of spikes with a pulse width up to 50 ns in Fast-mode and Fast-mode Plus. The user can disable this analog filter by setting the ANFOFF bit, and/or select a digital filter by configuring the DNF[3:0] bit in the I2C_CR1 register. When the digital filter is enabled, the level of the SCL or the SDA line is internally changed only if it remains stable for more than DNF x I2CCLK periods.
Page 702: I2C Timings
Inter-integrated circuit (I2C) interface RM0367 I2C timings The timings must be configured in order to guarantee a correct data hold and setup time, used in master and slave modes. This is done by programming the PRESC[3:0], SCLDEL[3:0] and SDADEL[3:0] bits in the I2C_TIMINGR register. The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C configuration window Figure 214.
Page 703 RM0367 Inter-integrated circuit (I2C) interface • When the SCL falling edge is internally detected, a delay is inserted before sending SDA output. This delay is where = SDADEL x t = (PRESC+1) SDADEL PRESC I2CCLK PRESC I2CCLK impacts the hold time SDADEL HD;DAT.
Page 704 Inter-integrated circuit (I2C) interface RM0367 Note: At every clock pulse, after SCL falling edge detection, the I2C master or slave stretches SCL low during at least [(SDADEL+SCLDEL+1) x (PRESC+1) + 1] x t , in both transmission I2CCLK and reception modes. In transmission mode, in case the data is not yet written in I2C_TXDR when SDADEL counter is finished, the I2C keeps on stretching SCL low until the next data is written.
Page 705: Software Reset
RM0367 Inter-integrated circuit (I2C) interface Figure 215. I2C initialization flowchart Initial settings Clear PE bit in I2C_CR1 Configure ANFOFF and DNF[3:0] in I2C_CR1 Configure PRESC[3:0], SDADEL[3:0], SCLDEL[3:0], SCLH[7:0], SCLL[7:0] in I2C_TIMINGR Configure NOSTRETCH in I2C_CR1 Set PE bit in I2C_CR1 MS19847V2 28.4.7 Software reset...
Page 706: Data Transfer
Inter-integrated circuit (I2C) interface RM0367 28.4.8 Data transfer The data transfer is managed through transmit and receive data registers and a shift register. Reception The SDA input fills the shift register. After the 8th SCL pulse (when the complete data byte is received), the shift register is copied into I2C_RXDR register if it is empty (RXNE=0).
Page 707: Figure 217. Data Transmission
RM0367 Inter-integrated circuit (I2C) interface Transmission If the I2C_TXDR register is not empty (TXE=0), its content is copied into the shift register after the 9th SCL pulse (the Acknowledge pulse). Then the shift register content is shifted out on SDA line. If TXE=1, meaning that no data is written yet in I2C_TXDR, SCL line is stretched low until I2C_TXDR is written.
Page 708: Table 127. I2C Configuration
Inter-integrated circuit (I2C) interface RM0367 When RELOAD=0 in master mode, the counter can be used in 2 modes: • Automatic end mode (AUTOEND = ‘1’ in the I2C_CR2 register). In this mode, the master automatically sends a STOP condition once the number of bytes programmed in the NBYTES[7:0] bit field is transferred.
Page 709 RM0367 Inter-integrated circuit (I2C) interface By default, the slave uses its clock stretching capability, which means that it stretches the SCL signal at low level when needed, in order to perform software actions. If the master does not support clock stretching, the I2C must be configured with NOSTRETCH=1 in the I2C_CR1 register.
Page 710: Figure 218. Slave Initialization Flowchart
Inter-integrated circuit (I2C) interface RM0367 Slave byte control mode In order to allow byte ACK control in slave reception mode, The Slave byte control mode must be enabled by setting the SBC bit in the I2C_CR1 register. This is required to be compliant with SMBus standards.
Page 711 RM0367 Inter-integrated circuit (I2C) interface For code example, refer to A.16.1: I2C configured in slave mode code example. Slave transmitter A transmit interrupt status (TXIS) is generated when the I2C_TXDR register becomes empty. An interrupt is generated if the TXIE bit is set in the I2C_CR1 register. The TXIS bit is cleared when the I2C_TXDR register is written with the next data byte to be transmitted.
Page 712: Figure 219. Transfer Sequence Flowchart For I2C Slave Transmitter
Inter-integrated circuit (I2C) interface RM0367 Figure 219. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH= 0 Slave transmission Slave initialization I2C_ISR.ADDR stretched Read ADDCODE and DIR in I2C_ISR Optional: Set I2C_ISR.TXE = 1 Set I2C_ICR.ADDRCF I2C_ISR.TXIS Write I2C_TXDR.TXDATA MS19851V2 712/1043 RM0367 Rev 7...
Page 713: Figure 220. Transfer Sequence Flowchart For I2C Slave Transmitter
RM0367 Inter-integrated circuit (I2C) interface Figure 220. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH= 1 Slave transmission Slave initialization I2C_ISR.STOPF I2C_ISR.TXIS Write I2C_TXDR.TXDATA Optional: Set I2C_ISR.TXE = 1 and I2C_ISR.TXIS=1 Set I2C_ICR.STOPCF MS19852V2 RM0367 Rev 7 713/1043...
Page 714: Figure 221. Transfer Bus Diagrams For I2C Slave Transmitter
Inter-integrated circuit (I2C) interface RM0367 Figure 221. Transfer bus diagrams for I2C slave transmitter legend: Example I2C slave transmitter 3 bytes with 1st data flushed, NOSTRETCH=0: transmission ADDR TXIS TXIS TXIS TXIS reception SCL stretch Address data3 data1 data2 EV4 EV5 EV1: ADDR ISR: check ADDCODE and DIR, set TXE, set ADDRCF EV2: TXIS ISR: wr data1 EV3: TXIS ISR: wr data2...
Page 715: Figure 222. Transfer Sequence Flowchart For Slave Receiver With Nostretch=0
RM0367 Inter-integrated circuit (I2C) interface Slave receiver RXNE is set in I2C_ISR when the I2C_RXDR is full, and generates an interrupt if RXIE is set in I2C_CR1. RXNE is cleared when I2C_RXDR is read. When a STOP is received and STOPIE is set in I2C_CR1, STOPF is set in I2C_ISR and an interrupt is generated.
Page 716: Figure 223. Transfer Sequence Flowchart For Slave Receiver With Nostretch=1
Inter-integrated circuit (I2C) interface RM0367 Figure 223. Transfer sequence flowchart for slave receiver with NOSTRETCH=1 Slave reception Slave initialization I2C_ISR.STOPF I2C_ISR.RXNE Set I2C_ICR.STOPCF Read I2C_RXDR.RXDATA MS19856V2 Figure 224. Transfer bus diagrams for I2C slave receiver legend: Example I2C slave receiver 3 bytes, NOSTRETCH=0: transmission ADDR RXNE...
Page 717 RM0367 Inter-integrated circuit (I2C) interface 28.4.10 I2C master mode I2C master initialization Before enabling the peripheral, the I2C master clock must be configured by setting the SCLH and SCLL bits in the I2C_TIMINGR register. The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C Configuration window.
Page 718: Figure 225. Master Clock Generation
Inter-integrated circuit (I2C) interface RM0367 Figure 225. Master clock generation SCL master clock generation SCL high level detected SCLH counter starts SCLH SYNC2 SCLL SYNC1 SCL low level detected SCL released SCLL counter starts SCL driven low SCL master clock synchronization SCL high level detected SCL high level detected SCL high level detected...
Page 719: Table 128. I2C-Smbus Specification Clock Timings
RM0367 Inter-integrated circuit (I2C) interface Table 128. I C-SMBus specification clock timings Standard- Fast-mode Fast-mode SMBus mode (Sm) (Fm) Plus (Fm+) Symbol Parameter Unit SCL clock frequency 1000 Hold time (repeated) START condition 0.26 µs HD:STA Set-up time for a repeated START 0.26 µs SU:STA...
Page 720: Figure 226. Master Initialization Flowchart
Inter-integrated circuit (I2C) interface RM0367 master re-launches automatically the slave address transmission until ACK is received. In this case ADDRCF must be set if a NACK is received from the slave, in order to stop sending the slave address. If the I2C is addressed as a slave (ADDR=1) while the START bit is set, the I2C switches to slave mode and the START bit is cleared, when the ADDRCF bit is set.
Page 721: Figure 228. 10-Bit Address Read Access With Head10R=1
RM0367 Inter-integrated circuit (I2C) interface • If the master addresses a 10-bit address slave, transmits data to this slave and then reads data from the same slave, a master transmission flow must be done first. Then a repeated start is set with the 10 bit slave address configured with HEAD10R=1. In this case the master sends this sequence: ReStart + Slave address 10-bit header Read.
Page 722: Figure 229. Transfer Sequence Flowchart For I2C Master Transmitter For N≤255 Bytes
Inter-integrated circuit (I2C) interface RM0367 Figure 229. Transfer sequence flowchart for I2C master transmitter for N≤255 bytes Master transmission Master initialization NBYTES = N AUTOEND = 0 for RESTART; 1 for STOP Configure slave address Set I2C_CR2.START I2C_ISR.TXIS I2C_ISR.NACKF = Write I2C_TXDR NBYTES transmitted?
Page 723: Figure 230. Transfer Sequence Flowchart For I2C Master Transmitter For N>255 Bytes
RM0367 Inter-integrated circuit (I2C) interface Figure 230. Transfer sequence flowchart for I2C master transmitter for N>255 bytes Master transmission Master initialization NBYTES = 0xFF; N=N-255 RELOAD = 1 Configure slave address Set I2C_CR2.START I2C_ISR.TXIS I2C_ISR.NACKF = 1? = 1? Write I2C_TXDR NBYTES transmitted I2C_ISR.TC...
Page 724: Figure 231. Transfer Bus Diagrams For I2C Master Transmitter
Inter-integrated circuit (I2C) interface RM0367 Figure 231. Transfer bus diagrams for I2C master transmitter Example I2C master transmitter 2 bytes, automatic end mode (STOP) legend: TXIS TXIS transmission reception Address data1 data2 SCL stretch INIT EV1 EV2 NBYTES INIT: program Slave address, program NBYTES = 2, AUTOEND=1, set START EV1: TXIS ISR: wr data1 EV2: TXIS ISR: wr data2 Example I2C master transmitter 2 bytes, software end mode (RESTART)
Page 725 RM0367 Inter-integrated circuit (I2C) interface Master receiver In the case of a read transfer, the RXNE flag is set after each byte reception, after the 8th SCL pulse. An RXNE event generates an interrupt if the RXIE bit is set in the I2C_CR1 register.
Page 726: Figure 232. Transfer Sequence Flowchart For I2C Master Receiver For N≤255 Bytes
Inter-integrated circuit (I2C) interface RM0367 Figure 232. Transfer sequence flowchart for I2C master receiver for N≤255 bytes Master reception Master initialization NBYTES = N AUTOEND = 0 for RESTART; 1 for STOP Configure slave address Set I2C_CR2.START I2C_ISR.RXNE Read I2C_RXDR NBYTES received? I2C_ISR.TC =...
Page 727: Figure 233. Transfer Sequence Flowchart For I2C Master Receiver For N >255 Bytes
RM0367 Inter-integrated circuit (I2C) interface Figure 233. Transfer sequence flowchart for I2C master receiver for N >255 bytes Master reception Master initialization NBYTES = 0xFF; N=N-255 RELOAD =1 Configure slave address Set I2C_CR2.START I2C_ISR.RXNE Read I2C_RXDR NBYTES received? I2C_ISR.TC = Set I2C_CR2.START with slave addess NBYTES ...
Page 728: Figure 234. Transfer Bus Diagrams For I2C Master Receiver
Inter-integrated circuit (I2C) interface RM0367 Figure 234. Transfer bus diagrams for I2C master receiver Example I2C master receiver 2 bytes, automatic end mode (STOP) RXNE RXNE legend: transmission Address data1 data2 reception INIT SCL stretch NBYTES INIT: program Slave address, program NBYTES = 2, AUTOEND=1, set START EV1: RXNE ISR: rd data1 EV2: RXNE ISR: rd data2 Example I2C master receiver 2 bytes, software end mode (RESTART)
Page 729: Table 129. Examples Of Timing Settings For Fi2Cclk = 8 Mhz
RM0367 Inter-integrated circuit (I2C) interface 28.4.11 I2C_TIMINGR register configuration examples The tables below provide examples of how to program the I2C_TIMINGR to obtain timings compliant with the I C specification. In order to get more accurate configuration values, the STM32CubeMX tool (I2C Configuration window) must be used. Table 129.
Page 730 Inter-integrated circuit (I2C) interface RM0367 2. t minimum value is 4 x t = 250 ns. Example with t = 1000 ns. SYNC1 + SYNC2 I2CCLK SYNC1 + SYNC2 minimum value is 4 x t = 250 ns. Example with t = 750 ns.
Page 731: Table 131. Smbus Timeout Specifications
RM0367 Inter-integrated circuit (I2C) interface Received command and data acknowledge control A SMBus receiver must be able to NACK each received command or data. In order to allow the ACK control in slave mode, the Slave Byte Control mode must be enabled by setting SBC bit in I2C_CR1 register.
Page 732: Figure 235. Timeout Intervals For T
Inter-integrated circuit (I2C) interface RM0367 Table 131. SMBus timeout specifications (continued) Limits Symbol Parameter Unit Cumulative clock low extend time (slave device) LOW:SEXT Cumulative clock low extend time (master device) LOW:MEXT 1. t is the cumulative time a given slave device is allowed to extend the clock cycles in one message LOW:SEXT from the initial START to the STOP.
Page 733 RM0367 Inter-integrated circuit (I2C) interface Bus idle detection A master can assume that the bus is free if it detects that the clock and data signals have been high for t greater than t . (refer to Table 126: I2C-SMBus specification data IDLE HIGH setup and hold...
Page 734: Table 132. Smbus With Pec Configuration
Inter-integrated circuit (I2C) interface RM0367 Table 132. SMBus with PEC configuration Mode SBC bit RELOAD bit AUTOEND bit PECBYTE bit Master Tx/Rx NBYTES + PEC+ STOP Master Tx/Rx NBYTES + PEC + ReSTART Slave Tx/Rx with PEC Timeout detection The timeout detection is enabled by setting the TIMOUTEN and TEXTEN bits in the I2C_TIMEOUTR register.
Page 735: Table 133. Examples Of Timeouta Settings For Various I2Cclk Frequencies
RM0367 Inter-integrated circuit (I2C) interface Caution: Changing the TIMEOUTA and TIDLE configuration is not allowed when the TIMEOUTEN is set. SMBus: 28.4.14 I2C_TIMEOUTR register configuration examples This section is relevant only when SMBus feature is supported. Refer to Section 28.3: I2C implementation.
Page 736: Figure 236. Transfer Sequence Flowchart For Smbus Slave Transmitter N Bytes + Pec
Inter-integrated circuit (I2C) interface RM0367 that case the total number of TXIS interrupts is NBYTES-1 and the content of the I2C_PECR register is automatically transmitted if the master requests an extra byte after the NBYTES-1 data transfer. Caution: The PECBYTE bit has no effect when the RELOAD bit is set. Figure 236.
Page 737: Figure 237. Transfer Bus Diagrams For Smbus Slave Transmitter (Sbc=1)
RM0367 Inter-integrated circuit (I2C) interface Figure 237. Transfer bus diagrams for SMBus slave transmitter (SBC=1) legend: Example SMBus slave transmitter 2 bytes + PEC, transmission ADDR TXIS TXIS reception SCL stretch Address data1 data2 NBYTES EV1: ADDR ISR: check ADDCODE, program NBYTES=3, set PECBYTE, set ADDRCF EV2: TXIS ISR: wr data1 EV3: TXIS ISR: wr data2 MS19869V2...
Page 738: Figure 238. Transfer Sequence Flowchart For Smbus Slave Receiver N Bytes + Pec
Inter-integrated circuit (I2C) interface RM0367 Figure 238. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC SMBus slave reception Slave initialization I2C_ISR.ADDR = Read ADDCODE and DIR in I2C_ISR stretched I2C_CR2.NBYTES = 1, RELOAD =1 PECBYTE=1 Set I2C_ICR.ADDRCF I2C_ISR.RXNE =1? I2C_ISR.TCR = 1? Read I2C_RXDR.RXDATA...
Page 739: Figure 239. Bus Transfer Diagrams For Smbus Slave Receiver (Sbc=1)
RM0367 Inter-integrated circuit (I2C) interface Figure 239. Bus transfer diagrams for SMBus slave receiver (SBC=1) legend: Example SMBus slave receiver 2 bytes + PEC transmission ADDR RXNE RXNE RXNE reception Address data1 data2 SCL stretch NBYTES EV1: ADDR ISR: check ADDCODE and DIR, program NBYTES = 3, PECBYTE=1, RELOAD=0, set ADDRCF EV2: RXNE ISR: rd data1 EV3: RXNE ISR: rd data2 EV4: RXNE ISR: rd PEC...
Page 740: Figure 240. Bus Transfer Diagrams For Smbus Master Transmitter
Inter-integrated circuit (I2C) interface RM0367 When the SMBus master wants to send a RESTART condition after the PEC, software mode must be selected (AUTOEND=0). In this case, once NBYTES-1 have been transmitted, the I2C_PECR register content is transmitted and the TC flag is set after the PEC transmission, stretching the SCL line low.
Page 741 RM0367 Inter-integrated circuit (I2C) interface SMBus master receiver When the SMBus master wants to receive the PEC followed by a STOP at the end of the transfer, automatic end mode can be selected (AUTOEND=1). The PECBYTE bit must be set and the slave address must be programmed, before setting the START bit. In this case, after NBYTES-1 data have been received, the next received byte is automatically checked versus the I2C_PECR register content.
Page 742: Figure 241. Bus Transfer Diagrams For Smbus Master Receiver
Inter-integrated circuit (I2C) interface RM0367 Figure 241. Bus transfer diagrams for SMBus master receiver Example SMBus master receiver 2 bytes + PEC, automatic end mode (STOP) RXNE RXNE RXNE legend: transmission data1 data2 Address reception INIT SCL stretch NBYTES INIT: program Slave address, program NBYTES = 3, AUTOEND=1, set PECBYTE, set START EV1: RXNE ISR: rd data1 EV2: RXNE ISR: rd data2 EV3: RXNE ISR: rd PEC...
Page 743 RM0367 Inter-integrated circuit (I2C) interface 28.4.16 Wakeup from Stop mode on address match This section is relevant only when wakeup from Stop mode feature is supported. Refer to Section 28.3: I2C implementation. The I2C is able to wakeup the MCU from Stop mode (APB clock is off), when it is addressed.
Page 744 Inter-integrated circuit (I2C) interface RM0367 Arbitration lost (ARLO) An arbitration loss is detected when a high level is sent on the SDA line, but a low level is sampled on the SCL rising edge. • In master mode, arbitration loss is detected during the address phase, data phase and data acknowledge phase.
Page 745 RM0367 Inter-integrated circuit (I2C) interface When a timeout violation is detected in master mode, a STOP condition is automatically sent. When a timeout violation is detected in slave mode, SDA and SCL lines are automatically released. When a timeout error is detected, the TIMEOUT flag is set in the I2C_ISR register, and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.
Page 746: Table 136. Effect Of Low-Power Modes On The I2C
Inter-integrated circuit (I2C) interface RM0367 Reception using DMA DMA (direct memory access) can be enabled for reception by setting the RXDMAEN bit in the I2C_CR1 register. Data is loaded from the I2C_RXDR register to an SRAM area configured using the DMA peripheral (refer to Section 11: Direct memory access controller (DMA) on page 265) whenever the RXNE bit is set.
Page 747: Table 137. I2C Interrupt Requests
RM0367 Inter-integrated circuit (I2C) interface 28.6 I2C interrupts The table below gives the list of I2C interrupt requests. Table 137. I2C Interrupt requests Exit the Exit the Exit the Interrupt Interrupt Event Enable Interrupt clear Sleep Stop Standby acronym event flag control bit method...
Page 748 Inter-integrated circuit (I2C) interface RM0367 28.7 I2C registers Refer to Section 1.2 on page 52 for a list of abbreviations used in register descriptions. The peripheral registers are accessed by words (32-bit). 28.7.1 I2C control register 1 (I2C_CR1) Address offset: 0x00 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing.
Page 749 RM0367 Inter-integrated circuit (I2C) interface Bit 19 GCEN: General call enable 0: General call disabled. Address 0b00000000 is NACKed. 1: General call enabled. Address 0b00000000 is ACKed. Bit 18 WUPEN: Wakeup from Stop mode enable 0: Wakeup from Stop mode disable. 1: Wakeup from Stop mode enable.
Page 750 Inter-integrated circuit (I2C) interface RM0367 Bit 7 ERRIE: Error interrupts enable 0: Error detection interrupts disabled 1: Error detection interrupts enabled Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT) Bit 6 TCIE: Transfer Complete interrupt enable...
Page 751 RM0367 Inter-integrated circuit (I2C) interface 28.7.2 I2C control register 2 (I2C_CR2) Address offset: 0x04 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 752 Inter-integrated circuit (I2C) interface RM0367 Bit 15 NACK: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. 0: an ACK is sent after current received byte.
Page 753 RM0367 Inter-integrated circuit (I2C) interface Bits 9:0 SADD[9:0]: Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent.
Page 754 Inter-integrated circuit (I2C) interface RM0367 28.7.4 I2C own address 2 register (I2C_OAR2) Address offset: 0x0C Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 755 RM0367 Inter-integrated circuit (I2C) interface 28.7.5 I2C timing register (I2C_TIMINGR) Address offset: 0x10 Reset value: 0x0000 0000 Access: No wait states PRESC[3:0] Res. Res. Res. Res. SCLDEL[3:0] SDADEL[3:0] SCLH[7:0] SCLL[7:0] Bits 31:28 PRESC[3:0]: Timing prescaler This field is used to prescale I2CCLK in order to generate the clock period t used for PRESC data setup and hold counters (refer to...
Page 756 Inter-integrated circuit (I2C) interface RM0367 28.7.6 I2C timeout register (I2C_TIMEOUTR) Address offset: 0x14 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 757 RM0367 Inter-integrated circuit (I2C) interface 28.7.7 I2C interrupt and status register (I2C_ISR) Address offset: 0x18 Reset value: 0x0000 0001 Access: No wait states Res. Res. Res. Res. Res. Res. Res. Res. ADDCODE[6:0] TIME BUSY Res. ALERT ARLO BERR STOPF NACKF ADDR RXNE TXIS Bits 31:24 Reserved, must be kept at reset value.
Page 758 Inter-integrated circuit (I2C) interface RM0367 Bit 11 PECERR: PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit.
Page 759 RM0367 Inter-integrated circuit (I2C) interface Bit 2 RXNE: Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE=0.
Page 760 Inter-integrated circuit (I2C) interface RM0367 Bit 10 OVRCF: Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register. Bit 9 ARLOCF: Arbitration lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. Bit 8 BERRCF: Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register.
Page 761 RM0367 Inter-integrated circuit (I2C) interface 28.7.10 I2C receive data register (I2C_RXDR) Address offset: 0x24 Reset value: 0x0000 0000 Access: No wait states Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 762: Table 138. I2C Register Map And Reset Values
Inter-integrated circuit (I2C) interface RM0367 28.7.12 I2C register map The table below provides the I2C register map and reset values. Table 138. I2C register map and reset values Register Offset name I2C_CR1 DNF[3:0] Reset value I2C_CR2 NBYTES[7:0] SADD[9:0] Reset value I2C_OAR1 OA1[9:0] Reset value...
Page 763 RM0367 Inter-integrated circuit (I2C) interface Table 138. I2C register map and reset values (continued) Register Offset name I2C_TXDR TXDATA[7:0] 0x28 Reset value Refer to Section 2.2 on page 58 for the register boundary addresses. RM0367 Rev 7 763/1043...
Page 764 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) 29.1 Introduction The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of Full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The USART offers a very wide range of baud rates using a programmable baud rate generator.
Page 765 RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) • Communication control/error detection flags • Parity control: – Transmits parity bit – Checks parity of received data byte • Fourteen interrupt sources with flags • Multiprocessor communications The USART enters Mute mode if the address does not match. •...
Page 766: Table 139. Stm32L0X3 Usart/Lpuart Features
Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 29.4 USART implementation Table 139. STM32L0x3 USART/LPUART features USART modes/features USART1/2 USART4 USART5 LPUART1 Hardware flow control for modem Continuous communication using DMA Multiprocessor communication Synchronous mode Smartcard mode Single-wire Half-duplex communication Ir SIR ENDEC block...
Page 767 RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) Serial data are transmitted and received through these pins in normal USART mode. The frames are comprised of: • An Idle Line prior to transmission or reception • A start bit • A data word (7, 8 or 9 bits) least significant bit first •...
Page 768: Figure 242. Usart Block Diagram
Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Figure 242. USART block diagram PRDATA PWDATA Write Read DR (data register) (CPU or DMA) (CPU or DMA) Transmit shift register Receive shift register IrDA Transmit data register Receive data register ENDEC (TDR) (RDR) block USART_GTPR register CK control...
Page 769 RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) 29.5.1 USART character description The word length can be selected as being either 7 or 8 or 9 bits by programming the M[1:0] bits in the USART_CR1 register (see Figure 243). • 7-bit character length: M[1:0] = 10 •...
Page 770: Figure 243. Word Length Programming
Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Figure 243. Word length programming 9-bit word length (M = 01 ), 1 Stop bit Possible Data frame Parity Next Start Stop Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Clock Start Idle frame Stop Stop...
Page 771 RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) 29.5.2 USART transmitter The transmitter can send data words of either 7, 8 or 9 bits depending on the M bits status. The Transmit Enable bit (TE) must be set in order to activate the transmitter function. The data in the transmit shift register is output on the TX pin and the corresponding clock pulses are output on the CK pin.
Page 772: Figure 244. Configurable Stop Bits
Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Figure 244. Configurable stop bits 8-bit data, 1 Stop bit Possible Data frame Next Next data frame parity bit start Stop Start bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 CLOCK ** LBCL bit controls last data clock pulse 8-bit data, 1 1/2 Stop bits Possible Data frame...
Page 773: Figure 245. Tc/Txe Behavior When Transmitting
RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) When a transmission is taking place, a write instruction to the USART_TDR register stores the data in the TDR register; next, the data is copied in the shift register at the end of the currently ongoing transmission.
Page 774: Figure 246. Start Bit Detection When Oversampling By 16 Or 8
Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 29.5.3 USART receiver The USART can receive data words of either 7, 8 or 9 bits depending on the M bits in the USART_CR1 register. Start bit detection The start bit detection sequence is the same when oversampling by 16 or by 8. In the USART, the start bit is detected when a specific sequence of samples is recognized.
Page 775 RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) If neither conditions a. or b. are met, the start detection aborts and the receiver returns to the idle state (no flag is set). Character reception During an USART reception, data shifts in least significant bit first (default configuration) through the RX pin.
Page 776 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Overrun error An overrun error occurs when a character is received when RXNE has not been reset. Data can not be transferred from the shift register to the RDR register until the RXNE bit is cleared.
Page 777: Figure 247. Data Sampling When Oversampling By 16
RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) Programming the ONEBIT bit in the USART_CR3 register selects the method used to evaluate the logic level. There are two options: • The majority vote of the three samples in the center of the received bit. In this case, when the 3 samples used for the majority vote are not equal, the NF bit is set •...
Page 778: Table 140. Noise Detection From Sampled Data
Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Figure 248. Data sampling when oversampling by 8 RX line sampled values Sample clock (x8) One bit time MSv31153V1 Table 140. Noise detection from sampled data Sampled value NE status Received bit value Framing error A framing error is detected when the stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise.
Page 779 RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) Configurable stop bits during reception The number of stop bits to be received can be configured through the control bits of Control Register 2 - it can be either 1 or 2 in normal mode and 0.5 or 1.5 in Smartcard mode. •...
Page 780 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 USARTDIV is an unsigned fixed point number that is coded on the USART_BRR register. • When OVER8 = 0, BRR = USARTDIV. • When OVER8 = 1 – BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. –...
Page 781: Table 141. Error Calculation For Programmed Baud Rates At F
RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) Table 141. Error calculation for programmed baud rates at f = 32 MHz in both cases of oversampling by 16 or by 8 Baud rate Oversampling by 16 (OVER8 = 0) Oversampling by 8 (OVER8 = 1) % Error = (Calculated - S.No...
Page 782: Table 142. Tolerance Of The Usart Receiver When Brr [3:0] = 0000
Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 where DWU is the error due to sampling point deviation when the wakeup from Stop mode is used. when M[1:0] = 01: WUUSART -------------------------- - × Tbit when M[1:0] = 00: WUUSART -------------------------- - ×...
Page 783 RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) Note: The data specified in Table 142 Table 143 may slightly differ in the special case when the received frames contain some Idle frames of exactly 10-bit durations when M bits = 00 (11-bit durations when M bits =01 or 9- bit durations when M bits = 10). 29.5.6 USART auto baud rate detection The USART is able to detect and automatically set the USART_BRR register value based...
Page 784 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 detection range (bit duration not between 16 and 65536 clock periods (oversampling by 16) and not between 8 and 65536 clock periods (oversampling by 8)). The RXNE interrupt will signal the end of the operation. At any later time, the auto baud rate detection may be relaunched by resetting the ABRF flag (by writing a 0).
Page 785: Figure 249. Mute Mode Using Idle Line Detection
RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) Idle line detection (WAKE=0) The USART enters mute mode when the MMRQ bit is written to 1 and the RWU is automatically set. It wakes up when an Idle frame is detected. Then the RWU bit is cleared by hardware but the IDLE bit is not set in the USART_ISR register.
Page 786: Figure 250. Mute Mode Using Address Mark Detection
Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Figure 250. Mute mode using address mark detection In this example, the current address of the receiver is 1 (programmed in the USART_CR2 register) RXNE RXNE RXNE IDLE Addr=0 Data 1 Data 2 IDLE Addr=1 Data 3 Data 4 Addr=2 Data 5 Mute mode Normal mode...
Page 787: Table 144. Frame Formats
RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) 29.5.9 USART parity control Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame length defined by the M bits, the possible USART frame formats are as listed in Table 144.
Page 788 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 29.5.10 USART LIN (local interconnection network) mode This section is relevant only when LIN mode is supported. Please refer to Section 29.4: USART implementation on page 766. The LIN mode is selected by setting the LINEN bit in the USART_CR2 register. In LIN mode, the following bits must be kept cleared: •...
Page 789: Figure 251. Break Detection In Lin Mode (11-Bit Break Length - Lbdl Bit Is Set)
RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) Figure 251. Break detection in LIN mode (11-bit break length - LBDL bit is set) Case 1: break signal not long enough => break discarded, LBDF is not set Break frame RX line Capture strobe Break state Idle Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10...
Page 790: Figure 252. Break Detection In Lin Mode Vs. Framing Error Detection
Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Figure 252. Break detection in LIN mode vs. Framing error detection Case 1: break occurring after an Idle RX line data 1 IDLE BREAK data 2 (0x55) data 3 (header) 1 data time 1 data time RXNE /FE LBDF Case 2: break occurring while data is being received...
Page 791: Figure 253. Usart Example Of Synchronous Transmission
RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) Note: The CK pin works in conjunction with the TX pin. Thus, the clock is provided only if the transmitter is enabled (TE=1) and data is being transmitted (the data register USART_TDR written). This means that it is not possible to receive synchronous data without transmitting data.
Page 792: Figure 255. Usart Data Clock Timing Diagram (M Bits = 01)
Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Figure 255. USART data clock timing diagram (M bits = 01) Idle or Idle or next preceding Start M bits =01 (9 data bits) Stop transmission transmission Clock (CPOL=0, CPHA=0) Clock (CPOL=0, CPHA=1) Clock (CPOL=1, CPHA=0) Clock (CPOL=1, CPHA=1)
Page 793 RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) 29.5.12 USART Single-wire Half-duplex communication Single-wire Half-duplex mode is selected by setting the HDSEL bit in the USART_CR3 register. In this mode, the following bits must be kept cleared: • LINEN and CLKEN bits in the USART_CR2 register, •...
Page 794: Figure 257. Iso 7816-3 Asynchronous Protocol
Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Figure 257. ISO 7816-3 asynchronous protocol Without Parity error Guard time Start bit WithParity error Guard time Start bit Line pulled low by receiver during stop in case of parity error MSv31162V1 When connected to a smartcard, the TX output of the USART drives a bidirectional line that is also driven by the smartcard.
Page 795: Figure 258. Parity Error Detection Using The 1.5 Stop Bits
RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) • In transmission, the USART inserts the Guard Time (as programmed in the Guard Time register) between two successive characters. As the Guard Time is measured after the stop bit of the previous character, the GT[7:0] register must be programmed to the desired CGT (Character Guard Time, as defined by the 7816-3 specification) minus 12 (the duration of one character).
Page 796 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Block mode (T=1) In T=1 (block) mode, the parity error transmission is deactivated, by clearing the NACK bit in the UART_CR3 register. When requesting a read from the smartcard, in block mode, the software must enable the receiver Timeout feature by setting the RTOEN bit in the USART_CR2 register and program the RTO bits field in the RTOR register to the BWT (block wait time) - 11 value.
Page 797 RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) Note: The error checking code (LRC/CRC) must be computed/verified by software. Direct and inverse convention The Smartcard protocol defines two conventions: direct and inverse. The direct convention is defined as: LSB first, logical bit value of 1 corresponds to a H state of the line and parity is even.
Page 798 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Method 2 The USART is programmed in 9-bit/no-parity mode, no bit inversion. In this mode it receives any of the two TS patterns as: (H) LHHL LLL LLH = 0x103 -> inverse convention to be chosen (H) LHHL HHH LLH = 0x13B ->...
Page 799: Figure 259. Irda Sir Endec- Block Diagram
RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) • The IrDA specification requires the acceptance of pulses greater than 1.41 µs. The acceptable pulse width is programmable. Glitch detection logic on the receiver end filters out pulses of width less than 2 PSC periods (PSC is the prescaler value programmed in the USART_GTPR).
Page 800: Figure 260. Irda Data Modulation (3/16) -Normal Mode
Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Figure 260. IrDA data modulation (3/16) -Normal Mode Stop Start IrDA_OUT Bit period 3/16 IrDA_IN MSv31165V1 29.5.15 USART continuous communication in DMA mode The USART is capable of performing continuous communication using the DMA. The DMA requests for Rx buffer and Tx buffer are generated independently.
Page 801: Figure 261. Transmission Using Dma
RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) In transmission mode, once the DMA has written all the data to be transmitted (the TCIF flag is set in the DMA_ISR register), the TC flag can be monitored to make sure that the USART communication is complete.
Page 802: Figure 262. Reception Using Dma
Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Figure 262. Reception using DMA Frame 2 Frame 1 Frame 3 TX line Set by hardware RXNE flag cleared by DMA read DMA request USART_RDR DMA reads USART_RDR Cleared DMA TCIF flag Set by hardware (transfer complete) software Software configures the...
Page 803: Figure 264. Rs232 Rts Flow Control
RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) RS232 RTS and CTS flow control can be enabled independently by writing the RTSE and CTSE bits respectively to 1 (in the USART_CR3 register). RS232 RTS flow control If the RTS flow control is enabled (RTSE=1), then RTS is asserted (tied low) as long as the USART receiver is ready to receive a new data.
Page 804: Figure 265. Rs232 Cts Flow Control
Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Figure 265. RS232 CTS flow control Transmit data register Data 2 empty Data 3 empty Stop Start Stop Start Idle Data 1 Data 2 Data 3 Writing data 3 in TDR Transmission of Data 3 is delayed until CTS = 0 MSv31167V2 Note:...
Page 805 RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) Note: If the USART kernel clock is kept ON during Stop mode, there is no constraint on the maximum baud rate that allows waking up from Stop mode. It is the same as in Run mode. •...
Page 806: Table 145. Effect Of Low-Power Modes On The Usart
Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Let us take this example: OVER8 = 0, M bits = 10, ONEBIT = 1, BRR [3:0] = 0000. In these conditions, according to Table 142: Tolerance of the USART receiver when BRR [3:0] = 0000, the USART receiver tolerance is 4.86 %.
Page 807: Figure 266. Usart Interrupt Mapping Diagram
RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) Table 146. USART interrupt requests (continued) Enable Control Interrupt event Event flag Idle line detected IDLE IDLEIE Parity error PEIE LIN break LBDF LBDIE Noise Flag, Overrun error and Framing Error in multibuffer NF or ORE or FE communication.
Page 808 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 29.8 USART registers Refer to Section 1.2 on page 52 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32 bits). 29.8.1 USART control register 1 (USART_CR1) Address offset: 0x00 Reset value: 0x0000 0000 Res.
Page 809 RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) Bits 20:16 DEDT[4:0]: Driver Enable de-assertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit duration, depending on the oversampling rate).
Page 810 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Bit 8 PEIE: PE interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A USART interrupt is generated whenever PE=1 in the USART_ISR register Bit 7 TXEIE: interrupt enable This bit is set and cleared by software.
Page 811 RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) Bit 2 RE: Receiver enable This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled 1: Receiver is enabled and begins searching for a start bit Bit 1 UESM: USART enable in Stop mode When this bit is cleared, the USART is not able to wake up the MCU from Stop mode.
Page 812 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Bits 31:28 ADD[7:4]: Address of the USART node This bit-field gives the address of the USART node or a character code to be recognized. This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7- bit address mark detection.
Page 813 RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) Bit 18 DATAINV: Binary data inversion This bit is set and cleared by software. 0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) 1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted.
Page 814 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Bit 11 CLKEN: Clock enable This bit allows the user to enable the CK pin. 0: CK pin disabled 1: CK pin enabled This bit can only be written when the USART is disabled (UE=0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value.
Page 815 RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) Bit 5 LBDL: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. 0: 10-bit break detection 1: 11-bit break detection This bit can only be written when the USART is disabled (UE=0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value.
Page 816 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Bits 21:20 WUS[1:0]: Wakeup from Stop mode interrupt flag selection This bit-field specify the event which activates the WUF (wakeup from Stop mode flag). 00: WUF active on address match (as defined by ADD[7:0] and ADDM7) 01:Reserved.
Page 817 RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) Bit 12 OVRDIS: Overrun Disable This bit is used to disable the receive overrun detection. 0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data. 1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register.
Page 818 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Bit 5 SCEN: Smartcard mode enable This bit is used for enabling Smartcard mode. 0: Smartcard Mode disabled 1: Smartcard Mode enabled This bit field can only be written when the USART is disabled (UE=0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value.
Page 819 RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) 29.8.4 USART baud rate register (USART_BRR) This register can only be written when the USART is disabled (UE=0). It may be automatically updated by hardware in auto baud rate detection mode. Address offset: 0x0C Reset value: 0x0000 0000 Res.
Page 820 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 GT[7:0]: Guard time value This bit-field is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value.
Page 821 RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) Bits 31:24 BLEN[7:0]: Block Length This bit-field gives the Block length in Smartcard T=1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0 ->...
Page 822 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Bits 31:5 Reserved, must be kept at reset value. Bit 4 TXFRQ: Transmit data flush request Writing 1 to this bit sets the TXE flag. This allows to discard the transmit data. This bit must be used only in Smartcard mode, when data has not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register.
Page 823 RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) Bit 22 REACK: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. When the wakeup from Stop mode is supported, the REACK flag can be used to verify that the USART is ready for reception before entering Stop mode.
Page 824 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Bit 15 ABRF: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE will also be set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE=1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register.
Page 825 RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) Bit 9 CTSIF: CTS interrupt flag This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE=1 in the USART_CR3 register.
Page 826 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Bit 4 IDLE: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register.
Page 827 RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) 29.8.9 USART interrupt flag clear register (USART_ICR) Address offset: 0x20 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WUCF Res. Res. CMCF Res. rc_w1 rc_w1 Res. Res. Res.
Page 828 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Bit 3 ORECF: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register. Bit 2 NCF: Noise detected clear flag Writing 1 to this bit clears the NF flag in the USART_ISR register. Bit 1 FECF: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register.
Page 829: Table 147. Usart Register Map And Reset Values
RM0367 Universal synchronous/asynchronous receiver transmitter (USART/UART) Bits 31:9 Reserved, must be kept at reset value. Bits 8:0 TDR[8:0]: Transmit data value Contains the data character to be transmitted. The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 242).
Page 830 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0367 Table 147. USART register map and reset values (continued) Offset Register USART_ISR 0x1C Reset value USART_ICR 0x20 Reset value USART_RDR RDR[8:0] 0x24 Reset value X X X X X X X X X USART_TDR TDR[8:0] 0x28 Reset value...
Page 831 RM0367 Low-power universal asynchronous receiver transmitter (LPUART) Low-power universal asynchronous receiver transmitter (LPUART) 30.1 Introduction The low-power universal asynchronous receiver transmitted (LPUART) is an UART which allows Full-duplex UART communications with a limited power consumption. Only 32.768 kHz LSE clock is required to allow UART communications up to 9600 baud. Higher baud rates can be reached when the LPUART is clocked by clock sources different from the LSE clock.
Page 832 The LPUART enters mute mode if the address does not match. • Wakeup from mute mode (by idle line detection or address mark detection) 30.3 LPUART implementation The STM32L0x3 devices embed one LPUART. Refer to Section 29.4: USART implementation for LPUART supported features. 832/1043...
Page 833: Table 148. Stm32L0X3 Usart/Lpuart Features
RM0367 Low-power universal asynchronous receiver transmitter (LPUART) Table 148. STM32L0x3 USART/LPUART features USART modes/features USART1/2 USART4 USART5 LPUART1 Hardware flow control for modem Continuous communication using DMA Multiprocessor communication Synchronous mode Smartcard mode Single-wire Half-duplex communication Ir SIR ENDEC block...
Page 834: Figure 267. Lpuart Block Diagram
Low-power universal asynchronous receiver transmitter (LPUART) RM0367 The following pins are required in RS232 Hardware flow control mode: • CTS: Clear To Send blocks the data transmission at the end of the current transfer when high • RTS: Request to send indicates that the LPUART is ready to receive data (when low). The following pin is required in RS485 Hardware control mode: •...
Page 835 RM0367 Low-power universal asynchronous receiver transmitter (LPUART) 30.4.1 LPUART character description Word length may be selected as being either 7 or 8 or 9 bits by programming the M[1:0] bits in the LPUART_CR1 register (see Figure 268). • 7-bit character length: M[1:0] = 10 •...
Page 836: Figure 268. Word Length Programming
Low-power universal asynchronous receiver transmitter (LPUART) RM0367 Figure 268. Word length programming 9-bit word length (M = 01 ), 1 Stop bit Possible Data frame Parity Next Start Stop Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Clock Start Idle frame Stop...
Page 837: Figure 269. Configurable Stop Bits
RM0367 Low-power universal asynchronous receiver transmitter (LPUART) 30.4.2 LPUART transmitter The transmitter can send data words of either 7 or 8 or 9 bits depending on the M bits status. The Transmit Enable bit (TE) must be set in order to activate the transmitter function. The data in the transmit shift register is output on the TX pin.
Page 838 Low-power universal asynchronous receiver transmitter (LPUART) RM0367 Character transmission procedure Program the M bits in LPUART_CR1 to define the word length. Select the desired baud rate using the LPUART_BRR register. Program the number of stop bits in LPUART_CR2. Enable the LPUART by writing the UE bit in LPUART_CR1 register to 1. Select DMA enable (DMAT) in LPUART_CR3 if multibuffer Communication is to take place.
Page 839: Figure 270. Tc/Txe Behavior When Transmitting
RM0367 Low-power universal asynchronous receiver transmitter (LPUART) Figure 270. TC/TXE behavior when transmitting Idle preamble Frame 1 Frame 2 Frame 3 TX line Set by hardware Set by hardware cleared by software cleared by software TXE flag Set by hardware LPUART_DR Set by hardware TC flag...
Page 840 Low-power universal asynchronous receiver transmitter (LPUART) RM0367 Character reception During an LPUART reception, data shifts in least significant bit first (default configuration) through the RX pin. In this mode, the LPUART_RDR register consists of a buffer (RDR) between the internal bus and the received shift register. Character reception procedure Program the M bits in LPUART_CR1 to define the word length.
Page 841 RM0367 Low-power universal asynchronous receiver transmitter (LPUART) Overrun error An overrun error occurs when a character is received when RXNE has not been reset. Data can not be transferred from the shift register to the RDR register until the RXNE bit is cleared.
Page 842 Low-power universal asynchronous receiver transmitter (LPUART) RM0367 Framing error A framing error is detected when the stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise. When the framing error is detected: •...
Page 843: Table 149. Error Calculation For Programmed Baud Rates At Fck = 32.768 Khz
RM0367 Low-power universal asynchronous receiver transmitter (LPUART) Table 149. Error calculation for programmed baud rates at f = 32.768 kHz = 32.768 kHz Baud rate Value programmed in the baud % Error = (Calculated - Desired) S.No Desired Actual rate register B.rate / Desired B.rate 300 baud 300 baud...
Page 844: Table 151. Tolerance Of The Lpuart Receiver
Low-power universal asynchronous receiver transmitter (LPUART) RM0367 30.4.5 Tolerance of the LPUART receiver to clock deviation The asynchronous receiver of the LPUART works correctly only if the total clock system deviation is less than the tolerance of the LPUART receiver. The causes which contribute to the total deviation are: •...
Page 845 RM0367 Low-power universal asynchronous receiver transmitter (LPUART) Table 151. Tolerance of the LPUART receiver (continued) M bits 768 ≤ BRR <1024 1024 ≤ BRR < 2048 2048 ≤ BRR < 4096 4096 ≤ BRR 8 bits (M=00), 2 stop bit 2.08% 2.86% 4.35%...
Page 846: Figure 271. Mute Mode Using Idle Line Detection
Low-power universal asynchronous receiver transmitter (LPUART) RM0367 Figure 271. Mute mode using Idle line detection RXNE RXNE Data 1 Data 2 Data 3 Data 4 IDLE Data 5 Data 6 Mute mode Normal mode MMRQ written to 1 Idle frame detected MSv31154V1 Note: If the MMRQ is set while the IDLE character has already elapsed, mute mode will not be...
Page 847: Table 152. Frame Formats
RM0367 Low-power universal asynchronous receiver transmitter (LPUART) Figure 272. Mute mode using address mark detection In this example, the current address of the receiver is 1 (programmed in the LPUART_CR2 register) RXNE RXNE RXNE IDLE Addr=0 Data 1 Data 2 IDLE Addr=1 Data 3 Data 4 Addr=2 Data 5 Mute mode...
Page 848 Low-power universal asynchronous receiver transmitter (LPUART) RM0367 Parity checking in reception If the parity check fails, the PE flag is set in the LPUART_ISR register and an interrupt is generated if PEIE is set in the LPUART_CR1 register. The PE flag is cleared by software writing 1 to the PECF in the LPUART_ICR register.
Page 849 RM0367 Low-power universal asynchronous receiver transmitter (LPUART) Transmission using DMA DMA mode can be enabled for transmission by setting DMAT bit in the LPUART_CR3 register. Data is loaded from a SRAM area configured using the DMA peripheral (refer to Section Direct memory access controller (DMA)) to the LPUART_TDR register whenever the TXE bit is set.
Page 850: Figure 273. Transmission Using Dma
Low-power universal asynchronous receiver transmitter (LPUART) RM0367 Figure 273. Transmission using DMA Idle preamble Frame 2 Frame 1 Frame 3 TX line Set by hardware cleared by Set by hardware cleared DMA read by DMA read TXE flag Set by hardware Ignored by the DMA because the transfer DMA request is complete...
Page 851: Figure 274. Reception Using Dma
RM0367 Low-power universal asynchronous receiver transmitter (LPUART) Figure 274. Reception using DMA Frame 2 Frame 1 Frame 3 TX line Set by hardware cleared by DMA read RXNE flag DMA request LPUART_RDR DMA reads LPUART_RDR Cleared by DMA TCIF flag Set by hardware software (transfer complete)
Page 852: Figure 276. Rs232 Rts Flow Control
Low-power universal asynchronous receiver transmitter (LPUART) RM0367 RS232 RTS flow control If the RTS flow control is enabled (RTSE=1), then RTS is asserted (tied low) as long as the LPUART receiver is ready to receive a new data. when the receive register is full, RTS is de- asserted, indicating that the transmission is expected to stop at the end of the current frame.
Page 853: Figure 277. Rs232 Cts Flow Control
RM0367 Low-power universal asynchronous receiver transmitter (LPUART) Figure 277. RS232 CTS flow control Transmit data register Data 2 empty Data 3 empty Stop Start Stop Start Idle Data 1 Data 2 Data 3 Writing data 3 in TDR Transmission of Data 3 is delayed until CTS = 0 MSv31167V2 Note:...
Page 854 Low-power universal asynchronous receiver transmitter (LPUART) RM0367 30.4.11 Wakeup from Stop mode using LPUART The LPUART is able to wake up the MCU from Stop modewhen the UESM bit is set and the LPUART clock is set to HSI or LSE (refer to the Reset and clock control (RCC) section. •...
Page 855 RM0367 Low-power universal asynchronous receiver transmitter (LPUART) Using Mute mode with Stop mode If the LPUART is put into Mute mode before entering Stop mode: • Wakeup from Mute mode on idle detection must not be used, because idle detection cannot work in Stop mode.
Page 856: Table 153. Effect Of Low-Power Modes On The Lpuart
Low-power universal asynchronous receiver transmitter (LPUART) RM0367 30.5 LPUART in low-power mode Table 153. Effect of low-power modes on the LPUART Mode Description Sleep No effect. USART interrupt causes the device to exit Sleep mode. Low-power run No effect. No effect. USART interrupt causes the device to exit Low-power sleep Low-power sleep mode.
Page 857: Figure 278. Lpuart Interrupt Mapping Diagram
RM0367 Low-power universal asynchronous receiver transmitter (LPUART) Figure 278. LPUART interrupt mapping diagram TCIE TXEIE CTSIF CTSIE IDLE IDLEIE LPUART RXNEIE interrupt RXNEIE RXNE PEIE LBDF LBDIE CMIE WUFIE MS31886V1 RM0367 Rev 7 857/1043...
Page 858 Low-power universal asynchronous receiver transmitter (LPUART) RM0367 30.7 LPUART registers Refer to Section 1.2 on page 52 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32 bits). 30.7.1 Control register 1 (LPUART_CR1) Address offset: 0x00 Reset value: 0x0000 Res.
Page 859 RM0367 Low-power universal asynchronous receiver transmitter (LPUART) Bit 13 MME: Mute mode enable This bit activates the mute mode function of the LPUART. When set, the LPUART can switch between the active and mute modes, as defined by the WAKE bit. It is set and cleared by software.
Page 860 Low-power universal asynchronous receiver transmitter (LPUART) RM0367 Bit 4 IDLEIE: IDLE interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An LPUART interrupt is generated whenever IDLE=1 in the LPUART_ISR register Bit 3 TE: Transmitter enable This bit enables the transmitter.
Page 861 RM0367 Low-power universal asynchronous receiver transmitter (LPUART) 30.7.2 Control register 2 (LPUART_CR2) Address offset: 0x04 Reset value: 0x0000 MSBFI ADD[7:4] ADD[3:0] Res. Res. Res. Res. DATAINV TXINV RXINV SWAP Res. STOP[1:0] Res. Res. Res. Res. Res. Res. Res. ADDM7 Res. Res.
Page 862 Low-power universal asynchronous receiver transmitter (LPUART) RM0367 Bit 16 RXINV: RX pin active level inversion This bit is set and cleared by software. 0: RX pin signal works using the standard logic levels (V =1/idle, Gnd=0/mark) 1: RX pin signal values are inverted. ((V =0/mark, Gnd=1/idle).
Page 863 RM0367 Low-power universal asynchronous receiver transmitter (LPUART) 30.7.3 Control register 3 (LPUART_CR3) Address offset: 0x08 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. UCESM WUFIE WUS[2:0] Res. Res. Res. Res. DDRE Res. CTSIE CTSE RTSE DMAT DMAR Res.
Page 864 Low-power universal asynchronous receiver transmitter (LPUART) RM0367 Bit 13 DDRE: DMA Disable on Reception Error 0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data will be transferred.
Page 865 RM0367 Low-power universal asynchronous receiver transmitter (LPUART) Bit 3 HDSEL: Half-duplex selection Selection of Single-wire Half-duplex mode 0: Half duplex mode is not selected 1: Half duplex mode is selected This bit can only be written when the LPUART is disabled (UE=0). Bits 2:1 Reserved, must be kept at reset value.
Page 866 Low-power universal asynchronous receiver transmitter (LPUART) RM0367 Bits 31:4 Reserved, must be kept at reset value Bit 3 RXFRQ: Receive data flush request Writing 1 to this bit clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition. Bit 2 MMRQ: Mute mode request Writing 1 to this bit puts the LPUART in mute mode and resets the RWU flag.
Page 867 RM0367 Low-power universal asynchronous receiver transmitter (LPUART) Bit 19 RWU: Receiver wakeup from Mute mode This bit indicates if the LPUART is in mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) is selected by the WAKE bit in the LPUART_CR1 register.
Page 868 Low-power universal asynchronous receiver transmitter (LPUART) RM0367 Bit 7 TXE: Transmit data register empty This bit is set by hardware when the content of the LPUART_TDR register has been transferred into the shift register. It is cleared by a write to the LPUART_TDR register. An interrupt is generated if the TXEIE bit =1 in the LPUART_CR1 register.
Page 869 RM0367 Low-power universal asynchronous receiver transmitter (LPUART) Bit 2 NF: START bit Noise detection flag This bit is set by hardware when noise is detected on the START bit of a received frame. It is cleared by software, writing 1 to the NFCF bit in the LPUART_ICR register. 0: No noise is detected 1: Noise is detected Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit...
Page 870 Low-power universal asynchronous receiver transmitter (LPUART) RM0367 Bit 6 TCCF: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the LPUART_ISR register. Bit 5 Reserved, must be kept at reset value. Bit 4 IDLECF: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the LPUART_ISR register.
Page 871 RM0367 Low-power universal asynchronous receiver transmitter (LPUART) Bits 31:9 Reserved, must be kept at reset value. Bits 8:0 TDR[8:0]: Transmit data value Contains the data character to be transmitted. The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 242).
Page 872: Table 155. Lpuart Register Map And Reset Values
Low-power universal asynchronous receiver transmitter (LPUART) RM0367 30.7.10 LPUART register map The table below gives the LPUART register map and reset values. Table 155. LPUART register map and reset values Offset Register LPUART_ 0x00 Reset value LPUART_ STOP ADD[7:4] ADD[3:0] [1:0] 0x04 Reset value...
Page 873 RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) Serial peripheral interface/ inter-IC sound (SPI/I2S) 31.1 Introduction The SPI/I²S interface can be used to communicate with external devices using the SPI protocol or the I S audio protocol. SPI or I S mode is selectable by software. SPI mode is selected by default after a device reset.
Page 874: Table 156. Stm32L0X3 Spi Implementation
256 × F (where F is the audio sampling frequency) 31.2 SPI/I2S implementation This manual describes the full set of features implemented in SPI1 and SPI2. Table 156. STM32L0x3 SPI implementation Features SPI1 SPI2 Hardware CRC calculation I2S mode TI mode 1.
Page 875: Figure 279. Spi Block Diagram
RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) 31.3 SPI functional description 31.3.1 General description The SPI allows synchronous, serial communication between the MCU and external devices. Application software can manage the communication by polling the status flag or using dedicated SPI interrupt. The main elements of SPI and their interactions are shown in the following block diagram Figure 279.
Page 876: Figure 280. Full-Duplex Single Master/ Single Slave Application
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 31.3.2 Communications between one master and one slave The SPI allows the MCU to communicate using different configurations, depending on the device targeted and the application requirements. These configurations use 2 or 3 wires (with software NSS management) or 3 or 4 wires (with hardware NSS management).
Page 877: Figure 281. Half-Duplex Single Master/ Single Slave Application
RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 281. Half-duplex single master/ single slave application MISO MISO Rx shift register Tx shift register 1kΩ MOSI MOSI Tx shift register Rx shift register SPI clock generator Master Slave MSv39624V1 1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the pins can be left unused by the peripheral.
Page 878: Figure 282. Simplex Single Master/Single Slave Application
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 Figure 282. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) MISO MISO Rx shift register Tx shift register MOSI MOSI Tx shift register Rx shift register SPI clock generator Master Slave MSv39625V1...
Page 879: Figure 283. Master And Three Independent Slaves
RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) 31.3.3 Standard multi-slave communication In a configuration with two or more independent slaves, the master uses GPIO pins to manage the chip select lines for each slave (see Figure 283.). The master must select one of the slaves individually by pulling low the GPIO connected to the slave NSS input.
Page 880: Figure 284. Multi-Master Application
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 31.3.4 Multi-master communication Unless SPI bus is not designed for a multi-master capability primarily, the user can use build in feature which detects a potential conflict between two nodes trying to master the bus at the same time.
Page 881: Figure 285. Hardware/Software Slave Select Management
RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) – NSS output enable (SSM=0,SSOE = 1): this configuration is only used when the MCU is set as master. The NSS pin is managed by the hardware. The NSS signal is driven low as soon as the SPI is enabled in master mode (SPE=1), and is kept low until the SPI is disabled (SPE =0).
Page 882 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 31.3.6 Communication formats During SPI communication, receive and transmit operations are performed simultaneously. The serial clock (SCK) synchronizes the shifting and sampling of the information on the data lines. The communication format depends on the clock phase, the clock polarity and the data frame format.
Page 883: Figure 286. Data Clock Timing Diagram
RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 286. Data clock timing diagram CPHA =1 CPOL = 1 CPOL = 0 MOSI LSBit MSBit MISO LSBit MSBit (to slave) Capture strobe CPHA =0 CPOL = 1 CPOL = 0 MOSI LSBit MSBit MISO...
Page 884 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 31.3.7 SPI configuration The configuration procedure is almost the same for master and slave. For specific mode setups, follow the dedicated chapters. When a standard communication is to be initialized, perform these steps: Write proper GPIO registers: Configure GPIO for MOSI, MISO and SCK pins.
Page 885 RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) Refer to Section 31.3.11: Communication using DMA (direct memory addressing) for details on how to handle DMA. 31.3.9 Data transmission and reception procedures Rx and Tx buffers In reception, data are received and then stored into an internal Rx buffer while in transmission, data are first stored into an internal Tx buffer before being transmitted.
Page 886: Figure 287. Txe/Rxne/Bsy Behavior In Master / Full-Duplex Mode (Bidimode=0, Rxonly=0) In The Case Of Continuous Transfers
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 While the master can provide all the transactions in continuous mode (SCK signal is continuous), it has to respect slave capability to handle data flow and its content at anytime. When necessary, the master must slow down the communication and provide either a slower clock or separate frames or data sessions with sufficient delays.
Page 887: Figure 288. Txe/Rxne/Bsy Behavior In Slave / Full-Duplex Mode (Bidimode=0, Rxonly=0) In The Case Of Continuous Transfers
RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 288. TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in the case of continuous transfers Example in Slave mode with CPOL=1, CPHA=1 DATA 1 = 0xF1 DATA 2 = 0xF2 DATA 3 = 0xF3 MISO/MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hardware...
Page 888 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 Note: During discontinuous communications, there is a 2 APB clock period delay between the write operation to the SPI_DR register and BSY bit setting. As a consequence it is mandatory to wait first until TXE is set and then until BSY is cleared after writing the last data.
Page 889: Figure 289. Transmission Using Dma
RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) To close communication it is mandatory to follow these steps in order: Disable DMA streams for Tx and Rx in the DMA registers, if the streams are used. Disable the SPI by following the SPI disable procedure. Disable DMA Tx and Rx buffers by clearing the TXDMAEN and RXDMAEN bits in the SPI_CR2 register, if DMA Tx and/or DMA Rx are used.
Page 890: Figure 290. Reception Using Dma
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 Figure 290. Reception using DMA Example with CPOL=1, CPHA=1 DATA 1 = 0xA1 DATA 2 = 0xA2 DATA 3 = 0xA3 MISO/MOSI (in) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hardware clear by DMA read RXNE flag...
Page 891 RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) The BSY flag is cleared under any one of the following conditions: • When the SPI is correctly disabled • When a fault is detected in Master mode (MODF bit set to 1) •...
Page 892 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 CRC error (CRCERR) This flag is used to verify the validity of the value received when the CRCEN bit in the SPIx_CR1 register is set. The CRCERR flag in the SPIx_SR register is set if the value received in the shift register does not match the receiver SPIx_RXCRC value.
Page 893: Figure 291. Ti Mode Transfer
RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) Note: To detect TI frame errors in slave transmitter only mode by using the Error interrupt (ERRIE=1), the SPI must be configured in 2-line unidirectional mode by setting BIDIMODE and BIDIOE to 1 in the SPI_CR1 register. When BIDIMODE is set to 0, OVR is set to 1 because the data register is never read and error interrupts are always generated, while when BIDIMODE is set to 1, data are not received and OVR is never set.
Page 894 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 The received CRC is stored in the Rx buffer like any other data frame. A CRC-format transaction takes one more data frame to communicate at the end of data sequence. When the last CRC data is received, an automatic check is performed comparing the received value and the value in the SPIx_RXCRC register.
Page 895: Table 157. Spi Interrupt Requests
RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) 31.5 SPI interrupts During SPI communication an interrupts can be generated by the following events: • Transmit Tx buffer ready to be loaded • Data received in Rx buffer • Master mode fault •...
Page 896: Figure 292. I
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 31.6 S functional description 31.6.1 S general description The block diagram of the I S is shown in Figure 292. Figure 292. I S block diagram Address and data bus Tx buffer BSY OVR MODF TxE RxNE 16-bit SIDE...
Page 897 RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) The I S shares three common pins with the SPI: • SD: Serial Data (mapped on the MOSI pin) to transmit or receive the two time- multiplexed data channels (in half-duplex mode only). •...
Page 898: Figure 293. Full-Duplex Communication
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 Figure 293. Full-duplex communication MASTER full-duplex configurations STM32 STM32 MCK (O) MCK (O) spix_tx_dm spix_rx_dm SD (O) SD (I) SPI2Sx SPI2Sx (MASTER-TX) (MASTER-RX) CK (O) CK (O) External External WS (O) WS (O) slave slave device...
Page 899: Figure 294. I S Philips Protocol Waveforms (16/32-Bit Full Accuracy, Cpol = 0)
RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) The I S interface supports four audio standards, configurable using the I2SSTD[1:0] and PCMSYNC bits in the SPIx_I2SCFGR register. S Philips standard For this standard, the WS signal is used to indicate which channel is being transmitted. It is activated one CK clock cycle before the first bit (MSB) is available.
Page 900: Figure 296. Transmitting 0X8Eaa33
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 • In transmission mode: If 0x8EAA33 has to be sent (24-bit): Figure 296. Transmitting 0x8EAA33 First write to Data register Second write to Data register 0x8EAA 0x33XX Only the 8 MSB are sent to compare the 24 bits 8 LSBs have no meaning and can be anything...
Page 901: Figure 299. Example Of 16-Bit Data Frame Extended To 32-Bit Channel Frame
RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 299. Example of 16-bit data frame extended to 32-bit channel frame Only one access to SPIx_DR 0x76A3 MS19595V1 For transmission, each time an MSB is written to SPIx_DR, the TXE flag is set and its interrupt, if allowed, is generated to load the SPIx_DR register with the new value to send.
Page 902: Figure 302. Msb Justified 16-Bit Extended To 32-Bit Packet Frame With Cpol = 0
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 Figure 302. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 Transmission Reception 16-bit data 16-bit remaining 0 forced Channel left 32-bit Channel right MS30102V1 LSB justified standard This standard is similar to the MSB justified standard (no difference for the 16-bit and 32-bit full-accuracy frame formats).
Page 903: Figure 305. Operations Required To Transmit 0X3478Ae
RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) • In transmission mode: If data 0x3478AE have to be transmitted, two write operations to the SPIx_DR register are required by software or by DMA. The operations are shown below. Figure 305. Operations required to transmit 0x3478AE First write to Data register Second write to Data register conditioned by TXE=1...
Page 904: Figure 308. Example Of 16-Bit Data Frame Extended To 32-Bit Channel Frame
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 Figure 308. Example of 16-bit data frame extended to 32-bit channel frame Only one access to the SPIx-DR register 0x76A3 MS19598V1 In transmission mode, when a TXE event occurs, the application has to write the data to be transmitted (in this case 0x76A3).
Page 905: Figure 311. Audio Sampling Frequency Definition
RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) Note: For both modes (master and slave) and for both synchronizations (short and long), the number of bits between two consecutive pieces of data (and so two synchronization signals) needs to be specified (DATLEN and CHLEN bits in the SPIx_I2SCFGR register) even in slave mode.
Page 906: Table 158. Audio-Frequency Precision Using Standard 8 Mhz Hse
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 The audio sampling frequency may be 192 KHz, 96 kHz, 48 kHz, 44.1 kHz, 32 kHz, 22.05 kHz, 16 kHz, 11.025 kHz or 8 kHz (or any other value within this range). In order to reach the desired frequency, the linear divider needs to be programmed according to the formulas below: When the master clock is generated (MCKOE in the SPIx_I2SPR register is set):...
Page 907 RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) Table 158. Audio-frequency precision using standard 8 MHz HSE (continued) I2SxCLK Data I2SDIV I2SODD MCLK Target fs(Hz) Real f (kHz) Error (MHz) length 11025 11.363 3.0715% 8000 7.812 2.3428% 8000 7.812 2.3428% 31.6.5 S master mode The I S can be configured in master mode.
Page 908 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 set after each transfer from the Tx buffer to the shift register and an interrupt is generated if the TXEIE bit in the SPIx_CR2 register is set. For more details about the write operations depending on the I S Standard-mode selected, refer to Section 31.6.3: Supported audio...
Page 909 RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) • For all other combinations of DATLEN and CHLEN, whatever the audio mode selected through the I2SSTD bits, carry out the following sequence to switch off the I Wait for the second to last RXNE = 1 (n – 1) Then wait one I S clock cycle (using a software loop) Disable the I...
Page 910 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 For more details about the write operations depending on the I S Standard-mode selected, refer to Section 31.6.3: Supported audio protocols. To secure a continuous audio data transmission, it is mandatory to write the SPIx_DR register with the next data to transmit before the end of the current transmission.
Page 911 RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) The BSY flag is useful to detect the end of a transfer if the software needs to disable the I This avoids corrupting the last transfer. For this, the procedure described below must be strictly respected.
Page 912: Table 159. I
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 ERRIE bit in the SPIx_CR2 register is set. The UDR bit is cleared by a read operation on the SPIx_SR register. Overrun flag (OVR) This flag is set when data are received and the previous data have not yet been read from the SPIx_DR register.
Page 913 RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) 31.7 SPI and I S registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). In addition, SPI_DR can be accessed by 8-bit. Refer to Section 1.2 for a list of abbreviations used in register descriptions. 31.7.1 SPI control register 1 (SPI_CR1) (not used in I S mode)
Page 914 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 Bit 10 RXONLY: Receive only mode enable This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active. This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted.
Page 915 RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) Bit 2 MSTR: Master selection 0: Slave configuration 1: Master configuration Note: This bit should not be changed when communication is ongoing. It is not used in I S mode. Bit1 CPOL: Clock polarity 0: CK to 0 when idle 1: CK to 1 when idle Note: This bit should not be changed when communication is ongoing.
Page 916 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 Bit 2 SSOE: SS output enable 0: SS output is disabled in master mode and the cell can work in multimaster configuration 1: SS output is enabled in master mode and when the cell is enabled. The cell cannot work in a multimaster environment.
Page 917 RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) Bit 5 MODF: Mode fault 0: No mode fault occurred 1: Mode fault occurred This flag is set by hardware and reset by a software sequence. Refer to Section 31.4 on page 892 for the software sequence.
Page 918 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 31.7.4 SPI data register (SPI_DR) Address offset: 0x0C Reset value: 0x0000 DR[15:0] Bits 15:0 DR[15:0]: Data register Data received or to be transmitted. The data register is split into 2 buffers - one for writing (Transmit Buffer) and another one for reading (Receive buffer).
Page 919 RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) 31.7.6 SPI RX CRC register (SPI_RXCRCR) (not used in I S mode) Address offset: 0x14 Reset value: 0x0000 RXCRC[15:0] Bits 15:0 RXCRC[15:0]: Rx CRC register When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes.
Page 920 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 31.7.8 SPI_I S configuration register (SPI_I2SCFGR) Address offset: 0x1C Reset value: 0x0000 PCMSY Res. Res. Res. Res. I2SMOD I2SE I2SCFG Res. I2SSTD CKPOL DATLEN CHLEN Bits 15:12 Reserved, must be kept at reset value. Bit 11 I2SMOD: I2S mode selection 0: SPI mode is selected 1: I2S mode is selected...
Page 921 RM0367 Serial peripheral interface/ inter-IC sound (SPI/I2S) Bit 3 CKPOL: Steady state clock polarity 0: I S clock steady state is low level 1: I S clock steady state is high level Note: For correct operation, this bit should be configured when the I S is disabled.
Page 922: Table 160. Spi Register Map And Reset Values
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0367 31.7.10 SPI register map The table provides shows the SPI register map and reset values. Table 160. SPI register map and reset values Offset Register SPI_CR1 [2:0] 0x00 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI_CR2 0x04 Reset value...
Page 923: Table 161. Stm32L0X3 Usb Implementation
USB_DP line) 32.3 USB implementation Table 161 describes the USB implementation in the devices. Table 161. STM32L0x3 USB implementation USB features Number of endpoints Size of dedicated packet buffer memory SRAM 1024 bytes Dedicated packet buffer memory SRAM access scheme 2 x 16 bits / word USB 2.0 Link Power Management (LPM) support...
Page 924: Figure 313. Usb Peripheral Block Diagram
Universal serial bus full-speed device interface (USB) RM0367 32.4 USB functional description Figure 313 shows the block diagram of the USB peripheral. Figure 313. USB peripheral block diagram USB PHY USB clock (48 MHz) Embedded Analog pull-up PCLK transceiver Clock Control RX-TX registers and logic...
Page 925 RM0367 Universal serial bus full-speed device interface (USB) place. The data buffered by the USB peripheral is loaded in an internal 16-bit register and memory access to the dedicated buffer is performed. When all the data has been transferred, if needed, the proper handshake packet over the USB is generated or expected according to the direction of the transfer.
Page 926 Universal serial bus full-speed device interface (USB) RM0367 • Endpoint-Related Registers: Each endpoint has an associated register containing the endpoint type and its current status. For mono-directional/single-buffer endpoints, a single register can be used to implement two distinct endpoints. The number of registers is 8, allowing up to 16 mono-directional/single-buffer or up to 7 double-buffer endpoints in any combination.
Page 927 RM0367 Universal serial bus full-speed device interface (USB) 32.5.2 System and power-on reset Upon system and power-on reset, the first operation the application software should perform is to provide all required clock signals to the USB peripheral and subsequently de-assert its reset signal so to be able to access its registers.
Page 928: Figure 314. Packet Buffer Areas With Examples Of Buffer Description Table Locations
Universal serial bus full-speed device interface (USB) RM0367 back accesses. The USB peripheral logic uses a dedicated clock. The frequency of this dedicated clock is fixed by the requirements of the USB standard at 48 MHz, and this can be different from the clock used for the interface to the APB bus.
Page 929 RM0367 Universal serial bus full-speed device interface (USB) Each packet buffer is used either during reception or transmission starting from the bottom. The USB peripheral will never change the contents of memory locations adjacent to the allocated memory buffers; if a packet bigger than the allocated buffer length is received (buffer overrun condition) the data will be copied to the memory only up to the last available location.
Page 930 Universal serial bus full-speed device interface (USB) RM0367 indicating a flow control condition: the USB host will retry the transaction until it succeeds. It is mandatory to execute the sequence of operations in the above mentioned order to avoid losing the notification of a second IN transaction addressed to the same endpoint immediately following the one which triggered the CTR interrupt.
Page 931 RM0367 Universal serial bus full-speed device interface (USB) processed. After the received data is processed, the application software should set the STAT_RX bits to ‘11 (Valid) in the USB_EPnR, enabling further transactions. While the STAT_RX bits are equal to ‘10 (NAK), any OUT request addressed to that endpoint is NAKed, indicating a flow control condition: the USB host will retry the transaction until it succeeds.
Page 932 Universal serial bus full-speed device interface (USB) RM0367 32.5.3 Double-buffered endpoints All different endpoint types defined by the USB standard represent different traffic models, and describe the typical requirements of different kind of data transfer operations. When large portions of data are to be transferred between the host PC and the USB function, the bulk endpoint type is the most suited model.
Page 933: Table 162. Double-Buffering Buffer Flag Definition
RM0367 Universal serial bus full-speed device interface (USB) Table 162. Double-buffering buffer flag definition Buffer flag ‘Transmission’ endpoint ‘Reception’ endpoint DTOG DTOG_TX (USB_EPnR bit 6) DTOG_RX (USB_EPnR bit 14) SW_BUF USB_EPnR bit 14 USB_EPnR bit 6 The memory buffer which is currently being used by the USB peripheral is defined by DTOG buffer flag, while the buffer currently in use by application software is identified by SW_BUF buffer flag.
Page 934 Universal serial bus full-speed device interface (USB) RM0367 DBL_BUF setting, STAT bit pair is not affected by the transaction termination and its value remains ‘11 (Valid). However, as the token packet of a new transaction is received, the actual endpoint status will be masked as ‘10 (NAK) when a buffer conflict between the USB peripheral and the application software is detected (this condition is identified by DTOG and SW_BUF having the same value, see Table 163 on page...
Page 935: Table 164. Isochronous Memory Buffers Usage
RM0367 Universal serial bus full-speed device interface (USB) Table 164. Isochronous memory buffers usage Endpoint DTOG bit Packet buffer used by the Packet buffer used by the Type value USB peripheral application software ADDRn_TX_0 / COUNTn_TX_0 ADDRn_TX_1 / COUNTn_TX_1 buffer description table buffer description table locations.
Page 936: Table 165. Resume Event Detection
Universal serial bus full-speed device interface (USB) RM0367 The actual procedure used to suspend the USB peripheral is device dependent since according to the device composition, different actions may be required to reduce the total consumption. A brief description of a typical suspend procedure is provided below, focused on the USB- related aspects of the application software routine responding to the SUSP notification of the USB peripheral: Set the FSUSP bit in the USB_CNTR register to 1.
Page 937 RM0367 Universal serial bus full-speed device interface (USB) Table 165. Resume event detection (continued) [RXDP,RXDM] status Wakeup event Required resume software action “01” Root resume None “11” Not allowed (noise on bus) Go back in Suspend mode A device may require to exit from suspend mode as an answer to particular events not directly related to the USB protocol (e.g.
Page 938 Universal serial bus full-speed device interface (USB) RM0367 32.6 USB and USB SRAM registers The USB peripheral registers can be divided into the following groups: • Common Registers: Interrupt and Control registers • Endpoint Registers: Endpoint configuration and status The USB SRAM registers cover: •...
Page 939 RM0367 Universal serial bus full-speed device interface (USB) Bit 11 SUSPM: Suspend mode interrupt mask 0: Suspend Mode Request (SUSP) Interrupt disabled. 1: SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. Bit 10 RESETM: USB reset interrupt mask 0: RESET Interrupt disabled.
Page 940 Universal serial bus full-speed device interface (USB) RM0367 Bit 1 PDWN: Power down This bit is used to completely switch off all USB-related analog parts if it is required to completely disable the USB peripheral for any reason. When this bit is set, the USB peripheral is disconnected from the transceivers and it cannot be used.
Page 941 RM0367 Universal serial bus full-speed device interface (USB) could be set by the hardware and the next write will clear it before the microprocessor has the time to serve the event. The following describes each bit in detail: Bit 15 CTR: Correct transfer This bit is set by the hardware to indicate that an endpoint has successfully completed a transaction;...
Page 942 Universal serial bus full-speed device interface (USB) RM0367 Bit 10 RESET: USB reset request Set when the USB peripheral detects an active USB RESET signal at its inputs. The USB peripheral, in response to a RESET, just resets its internal protocol state machine, generating an interrupt if RESETM enable bit in the USB_CNTR register is set.
Page 943 RM0367 Universal serial bus full-speed device interface (USB) Bits 3:0 EP_ID[3:0]: Endpoint Identifier These bits are written by the hardware according to the endpoint number, which generated the interrupt request. If several endpoint transactions are pending, the hardware writes the endpoint identifier related to the endpoint having the highest priority defined in the following way: Two endpoint sets are defined, in order of priority: Isochronous and double-buffered bulk endpoints are considered first and then the other endpoints are examined.
Page 944 Universal serial bus full-speed device interface (USB) RM0367 Res. Res. Res. Res. Res. Res. Res. Res. ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 Bits 15:8 Reserved Bit 7 EF: Enable function This bit is set by the software to enable the USB device. The address of this device is contained in the following ADD[6:0] bits.
Page 945 RM0367 Universal serial bus full-speed device interface (USB) Bits 15:8 Reserved, must be kept at reset value. Bits 7:4 BESL[3:0]: BESL value These bits contain the BESL value received with last ACKed LPM Token Bit 3 REMWAKE: bRemoteWake value This bit contains the bRemoteWake value received with last ACKed LPM Token Bit 2 Reserved Bit 1 LPMACK: LPM Token acknowledge enable 0: the valid LPM Token will be NYET.
Page 946 Universal serial bus full-speed device interface (USB) RM0367 Bit 4 DCDET: Data contact detection (DCD) status This bit gives the result of DCD. 0: data lines contact not detected. 1: data lines contact detected. Bit 3 SDEN: Secondary detection (SD) mode enable This bit is set by the software to put the BCD into SD mode.
Page 947 RM0367 Universal serial bus full-speed device interface (USB) Bit 15 CTR_RX: Correct transfer for reception This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated.
Page 948 Universal serial bus full-speed device interface (USB) RM0367 Bits 10:9 EP_TYPE[1:0]: Endpoint type These bits configure the behavior of this endpoint as described in Table 167: Endpoint type encoding on page 949. Endpoint 0 must always be a control endpoint and each USB function must have at least one control endpoint which has address 0, but there may be other control endpoints if required.
Page 949: Table 166. Reception Status Encoding
RM0367 Universal serial bus full-speed device interface (USB) Bits 5:4 STAT_TX [1:0]: Status bits, for transmission transfers These bits contain the information about the endpoint status, listed in Table 169. These bits can be toggled by the software to initialize their value. When the application software writes ‘0, the value remains unchanged, while writing ‘1 makes the bit value toggle.
Page 950: Table 169. Transmission Status Encoding
Universal serial bus full-speed device interface (USB) RM0367 Table 169. Transmission status encoding STAT_TX[1:0] Meaning DISABLED: all transmission requests addressed to this endpoint are ignored. STALL: the endpoint is stalled and all transmission requests result in a STALL handshake. NAK: the endpoint is naked and all transmission requests result in a NAK handshake.
Page 951 RM0367 Universal serial bus full-speed device interface (USB) 32.6.2 Buffer descriptor table Note: The buffer descriptor table is located inside the packet buffer memory in the separate "USB SRAM" address space. Although the buffer descriptor table is located inside the packet buffer memory ("USB SRAM"...
Page 952 Universal serial bus full-speed device interface (USB) RM0367 Bits 15:10 These bits are not used since packet size is limited by USB specifications to 1023 bytes. Their value is not considered by the USB peripheral. Bits 9:0 COUNTn_TX[9:0]: Transmission byte count These bits contain the number of bytes to be transmitted by the endpoint associated with the USB_EPnR register at the next IN token addressed to it.
Page 953: Table 170. Definition Of Allocated Buffer Memory
RM0367 Universal serial bus full-speed device interface (USB) enumeration process according to its maxPacketSize parameter value (See “Universal Serial Bus Specification”). Bit 15 BL_SIZE: Block size This bit selects the size of memory block used to define the allocated buffer area. –...
Page 954: Table 171. Usb Register Map And Reset Values
Universal serial bus full-speed device interface (USB) RM0367 32.6.3 USB register map The table below provides the USB register map and reset values. Table 171. USB register map and reset values Offset Register STAT_ STAT_ USB_EP0R TYPE EA[3:0] 0x00 [1:0] [1:0] [1:0] Reset value...
Page 955 RM0367 Universal serial bus full-speed device interface (USB) Table 171. USB register map and reset values (continued) Offset Register USB_BTABLE BTABLE[15:3] 0x50 Reset value USB_LPMCSR BESL[3:0] 0x54 Reset value USB_BCDR 0x58 Reset value Refer to Section 2.2 on page 58 for the register boundary addresses.
Page 956: Figure 315. Block Diagram Of Stm32L0X3 Mcu And Cortex
The debug features are used by the debugger host when connecting to and debugging the STM32L0x3 MCUs. One interface for debug is available: • Serial wire ® Figure 315. Block diagram of STM32L0x3 MCU and Cortex -M0+-level debug support STM32 MCU debug suppo rt Cortex-M0 debug support Bus matrix System...
Page 957: Table 172. Sw Debug Port Pins
• CoreSight Design Kit revision r1p1 Technical Reference Manual 33.3 Pinout and debug port pins The STM32L0x3 MCUs are available in various packages with different numbers of available pins. 33.3.1 SWD port pins Two pins are used as outputs for the SW-DP as alternate functions of general purpose I/Os.
Page 958 33.4.1 MCU device ID code The STM32L0x3 products integrate an MCU ID code. This ID identifies the ST MCU part number and the die revision. This code is accessible by the software debug port (two pins) or by the user software.
Page 959: Table 174. Packet Request (8-Bits)
RM0367 Debug support (DBG) Table 173. REV-ID values REV_ID Cat. 3 devices Cat. 5 devices 0x1000 Rev A 0x1008 Rev Z 0x1018 Rev Y 0x1038 Rev X 0x2000 Rev B 0x2008 Rev Z 33.5 SWD port 33.5.1 SWD protocol introduction This synchronous serial protocol uses two pins: •...
Page 960: Table 175. Ack Response (3 Bits)
Debug support (DBG) RM0367 Table 174. Packet request (8-bits) (continued) Name Description Parity Single bit parity of preceding bits Stop Not driven by the host. Must be read as “1” by the target Park because of the pull-up ® Refer to the Cortex -M0+ TRM for a detailed description of DPACC and APACC registers.
Page 961: Table 177. Sw-Dp Registers
RM0367 Debug support (DBG) 33.5.4 DP and AP read/write accesses • Read accesses to the DP are not posted: the target response can be immediate (if ACK=OK) or can be delayed (if ACK=WAIT). • Read accesses to the AP are posted. This means that the result of the access is returned on the next transfer.
Page 962: Table 178. 32-Bit Debug Port Registers Addressed Through The Shifted Value A[3:2]
Debug support (DBG) RM0367 Table 177. SW-DP registers (continued) CTRLSEL bit A[3:2] of SELECT Register Notes register The purpose is to select the current access Write SELECT port and the active 4-words register window This read buffer is useful because AP accesses are posted (the result of a read AP request is available on the next AP transaction).
Page 963: Table 179. Core Debug Registers
RM0367 Debug support (DBG) 33.6 Core debug Core debug is accessed through the core debug registers. Debug access to these registers is by means of the debug access port. It consists of four registers: Table 179. Core debug registers Register Description The 32-bit Debug Halting Control and Status Register DHCSR...
Page 964 Debug support (DBG) RM0367 33.8 DWT (Data Watchpoint) ® The Cortex -M0+ DWT implementation provides two watchpoint register sets. 33.8.1 DWT functionality The processor watchpoints implement both data address and PC based watchpoint functionality, a PC sampling register, and support comparator address masking, as ®...
Page 965 RM0367 Debug support (DBG) 33.9.2 Debug support for timers, watchdog and I During a breakpoint, it is necessary to choose how the counter of timers and watchdog should behave: • They can continue to count inside a breakpoint. This is usually required when a PWM is controlling a motor, for example.
Page 966 Debug support (DBG) RM0367 Bits 31:3 Reserved, must be kept at reset value. Bit 2 DBG_STANDBY: Debug Standby mode 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. From software point of view, exiting from Standby is identical than fetching reset vector (except a few status bit indicated that the MCU is resuming from Standby) 1: (FCLK=On, HCLK=On) In this case, the digital part is not unpowered and FCLK and HCLK are provided by the internal RC oscillator which remains active.
Page 967 RM0367 Debug support (DBG) 33.9.4 Debug MCU APB1 freeze register (DBG_APB1_FZ) The DBG_APB1_FZ register is used to configure the following APB peripherals, when the MCU under debug: • Timer clock counter freeze • I2C SMBUS timeout freeze • System window watchdog and independent watchdog counter freeze support. This register is mapped at address 0x4001 5808.
Page 968 Debug support (DBG) RM0367 Bit 11 DBG_WWDG_STOP: Debug window watchdog stopped when core is halted 0: The window watchdog counter clock continues even if the core is halted 1: The window watchdog counter clock is stopped when the core is halted Bit 10 DBG_RTC_STOP: Debug RTC stopped when core is halted 0: The clock of the RTC counter is fed even if the core is halted 1: The clock of the RTC counter is stopped when the core is halted...
Page 969 RM0367 Debug support (DBG) 33.9.5 Debug MCU APB2 freeze register (DBG_APB2_FZ) The DBG_APB2_FZ register is used to configure some APB peripheral features when the MCU is under DEBUG: • Timer clock counter freeze. This register is mapped at address 0x4001580C. It is asynchronously reset by the POR (and not the system reset).
Page 970: Table 180. Dbg Register Map And Reset Values
Debug support (DBG) RM0367 33.10 DBG register map The following table summarizes the Debug registers. Table 180. DBG register map and reset values Addr. Register DBG_ REV_ID DEV_ID IDCODE Reset value X X X X X X X X X X X X X X X X X X X X X X X X X X X X DBG_CR Reset value...
Page 971 Device electronic signature Device electronic signature This section applies to all STM32L0x3 devices, unless otherwise specified. The electronic signature is stored in the System memory area in the Flash memory module, and can be read using the JTAG/SWD or the CPU. It contains factory-programmed identification data that allow the user firmware or other external devices to automatically match its interface to the characteristics of the STM32L0x3 microcontroller.
Page 972 Device electronic signature RM0367 Base address: 0x1FF8 0050 Address offset: 0x00 Read only = 0xXXXX XXXX where X is factory-programmed U_ID(31:16) U_ID(15:0) (31:24): Bits 31:0 U_ID WAF_NUM[7:0] Wafer number (8-bit unsigned number) (23:0): U_ID LOT_NUM[55:32] Lot number (ASCII code) Address offset: 0x04 Read only = 0xXXXX XXXX where X is factory-programmed U_ID(63:48) U_ID(47:32)
Page 973 This appendix shows the code examples of the sequence described in this Reference Manual. These code examples are extracted from the STM32L0xx Snippet firmware package STM32SnippetsL0 available on www.st.com. These code examples used the peripheral bit and register description from the CMSIS header file (stm32l0xx.h).
Page 974 Code examples RM0367 A.2.3 Switch from PLL to HSI16 sequence code uint32_t tickstart; /* (1) Switch the clock on HSI16/4 */ /* (2) Wait for clock switched on HSI16/4 */ /* (3) Disable the PLL by resetting PLLON */ /* (4) Wait until PLLRDY is cleared */ RCC->CFGR (RCC->CFGR &...
Page 975 RM0367 Code examples tickstart = Tick; & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) /* (4) */ while ((RCC->CFGR ((Tick tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) error = ERROR_CLKSWITCH_TIMEOUT; /* Report an error */ return; Note: Tick is a global variable incremented in the SysTick ISR each millisecond. NVM Operation code example A.3.1 Unlocking the data EEPROM and FLASH_PECR register...
Page 976 Code examples RM0367 /* For robust implementation, add here time-out management */ ((FLASH->PECR & FLASH_PECR_PELOCK) == 0) /* (2) */ ((FLASH->PECR & FLASH_PECR_PRGLOCK) != 0) /* (3) */ FLASH->PRGKEYR = FLASH_PRGKEY1; /* (4) */ FLASH->PRGKEYR = FLASH_PRGKEY2; A.3.4 Unlocking the option bytes area code example /* (1) Wait till no operation is on going */ /* (2) Check that the PELOCK is unlocked */ /* (3) Check if the OPTLOCK is unlocked */...
Page 977 RM0367 Code examples /* (3) Enter in wait for interrupt. The EOP check is done in the Flash ISR /* (6) Reset the ERASE and DATA bits in the FLASH_PECR register to disable the page erase */ FLASH->PECR FLASH_PECR_ERASE | FLASH_PECR_DATA; /* (1) */ *(__IO uint32_t *)addr = (uint32_t)0;...
Page 978 Code examples RM0367 * Retval None __INLINE __RAM_FUNC void OptionByteErase(uint8_t index) /* (1) Set the ERASE bit in the FLASH_PECR register to enable option byte erasing */ /* (2) Write a 32-bit word value at the option byte address to be erased to start the erase sequence */ /* (3) Wait until the BSY bit is reset in the FLASH_SR register */ /* (4) Check the EOP flag in the FLASH_SR register */...
Page 979 RM0367 Code examples else /* Manage the error cases */ A.3.10 Program half-page to Flash program memory code example * This function programs a half page. It is executed from the RAM. * The Programming bit (PROG) and half-page programming bit (FPRG) * is set at the beginning and reset at the end of the function, * in case of successive programming, these two operations * could be performed outside the function.
Page 980 Code examples RM0367 /* Manage the error cases */ FLASH->PECR &= ~(FLASH_PECR_PROG | FLASH_PECR_FPRG); /* (6) */ Note: This function must be loaded in RAM. A.3.11 Erase a page in Flash program memory code example * This function erases a page of flash. * The Page Erase bit (PER) is set at the beginning and reset * at the end of the function, in case of successive erase, * these two operations could be performed outside the function.
Page 981 RM0367 Code examples A.3.12 Mass erase code example * This function performs a mass erase of the flash. * This function is loaded in RAM. * Param None * Retval while successful, the function never returns except if executed from RAM __RAM_FUNC void FlashMassErase(void)
Page 982 Code examples RM0367 Clock Controller A.4.1 HSE start sequence code example * This function enables the interrupton HSE ready, * and start the HSE as external clock. * Param None * Retval None __INLINE StartHSE(void) void /* Configure NVIC for RCC */ /* (1) Enable Interrupt on RCC */ /* (2) Set priority for RCC */ NVIC_EnableIRQ(RCC_CRS_IRQn);...
Page 983 RM0367 Code examples /* Manage error */ A.4.2 PLL configuration modification code example /* (1) Test if PLL is used as System clock */ /* (2) Select HSI as system clock */ /* (3) Wait for HSI switched */ /* (4) Disable the PLL */ /* (5) Wait until PLLRDY is cleared */ /* (6) Set latency to 1 wait state */ /* (7) Set the PLL multiplier to 24 and divider by 3 */...
Page 984 Code examples RM0367 A.4.3 MCO selection code example /* (1) Clear the MCO selection bits */ /* (2)Select system clock/4 to be output on the MCO without prescaler */ RCC->CFGR &= (uint32_t) RCC_CFGR_MCOSEL; /* (1) */ RCC->CFGR RCC_CFGR_MCO_SYSCLK | RCC_CFGR_MCO_PRE_4; /* (2) */ GPIOs A.5.1...
Page 985 RM0367 Code examples A.6.1 DMA Channel Configuration sequence code example /* (1) Enable the peripheral clock on DMA */ /* (2) Remap DMA channel1 on ADC (reset value) */ /* (3) Enable DMA transfer on ADC */ /* (4) Configure the peripheral data register address */ /* (5) Configure the memory address */ /* (6) Configure the number of DMA tranfer to be performs on channel 1 */ /* (7) Configure increment, size and interrupts */...
Page 986 Code examples RM0367 /* (5) Configure the Trigger Selection bits of the Interrupt line on rising edge */ /* (6) Configure the Trigger Selection bits of the Interrupt line on falling edge */ RCC->IOPENR |= RCC_IOPENR_GPIOAEN; /* (1) */ GPIOA->MODER (GPIOA->MODER &...
Page 987 RM0367 Code examples & ADC_ISR_ADRDY) == 0) /* (3) */ while ((ADC1->ISR /* For robust implementation, add here time-out management */ A.8.3 ADC disable sequence code example /* (1) Ensure that no conversion on going */ /* (2) Stop any ongoing conversion */ /* (3) Wait until ADSTP is reset by hardware i.e.
Page 988 Code examples RM0367 /* Performs the AD conversion */ ADC1->CR |= ADC_CR_ADSTART; /* start the ADC conversion */ while ((ADC1->ISR & ADC_ISR_EOC) == 0) /* wait end of conversion */ /* For robust implementation, add here time-out management */ A.8.6 Continuous conversion sequence code example Software trigger /* (1) Select HSI16 by writing 00 in CKMODE (reset value) */...
Page 989 RM0367 Code examples A.8.8 Continuous conversion sequence code example Hardware trigger /* (1) Select HSI16 by writing 00 in CKMODE (reset value) */ /* (2) Select the external trigger on TIM22_TRGO (TRG4 i.e. EXTSEL = 100 and rising edge, the continuous mode and scanning direction */ /* (3) Select CHSEL4, CHSEL9 and CHSEL17 */ /* (4) Select a sampling mode of 111 i.e.
Page 990 Code examples RM0367 A.8.10 DMA circular mode sequence code example /* (1) Enable the peripheral clock on DMA */ /* (2) Enable DMA transfer on ADC and circular mode */ /* (3) Configure the peripheral data register address */ /* (4) Configure the memory address */ /* (5) Configure the number of DMA tranfer to be performs on DMA channel 1 */ /* (6) Configure increment, size, interrupts and circular mode */...
Page 991 RM0367 Code examples ADC1->CFGR1 ADC_CFGR1_EXTEN_0 ADC_CFGR1_EXTSEL_2 \ ADC_CFGR1_SCANDIR | ADC_CFGR1_AUTOFF; /* (2) */ ADC1->CHSELR ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL9 \ | ADC_CHSELR_CHSEL17; /* (3) */ ADC1->SMPR ADC_SMPR_SMP_0 ADC_SMPR_SMP_1 | ADC_SMPR_SMP_2; /* (4) */ ADC1->IER ADC_IER_EOCIE ADC_IER_EOSEQIE | ADC_IER_OVRIE; /* (5) */ ADC->CCR |= ADC_CCR_VREFEN; /* (6) */ A.8.13 Auto off and wait mode sequence code example...
Page 992 Code examples RM0367 /* (6) Enable interrupts on EOC, EOSEQ and Analog Watchdog */ /* (7) Wake-up the VREFINT (only for VBAT, Temp sensor and VRefInt) */ //ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */ ADC1->CFGR1 ADC_CFGR1_CONT \ | (17<<26) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL;...
Page 993 RM0367 Code examples - (int32_t) *TEMP30_CAL_ADDR temperature temperature - 30); (int32_t)(130 temperature temperature (int32_t)(*TEMP130_CAL_ADDR *TEMP30_CAL_ADDR); temperature temperature + 30; return(temperature); A.9.1 Independent trigger without wave generation code example /* (1) Enable the peripheral clock of the DAC */ /* (2) Configure WAVE1 at 01 and LFSR mask amplitude (MAMP1) at 1000 for a 511-bits amplitude, enable the DAC ch1, disable buffer on ch1,...
Page 994 Code examples RM0367 DAC->CR DAC_CR_DMAUDRIE1 DAC_CR_DMAEN1 DAC_CR_BOFF1 DAC_CR_TEN1 | DAC_CR_EN1; /* (2) */ /* (1) Enable the peripheral clock on DMA */ /* (2) Remap DAC on DMA channel 2 */ /* (3) Configure the peripheral data register address */ /* (4) Configure the memory address */ /* (5) Configure the number of DMA tranfer to be performs on DMA channel x */...
Page 995 RM0367 Code examples TSC->IOHCR &= (uint32_t)(~(TSC_IOHCR_G2_IO3 | TSC_IOHCR_G2_IO4)); /* (2) */ TSC->IER = TSC_IER_EOAIE; /* (3) */ TSC->IOSCR = TSC_IOSCR_G2_IO4; /* (4) */ TSC->IOCCR = TSC_IOCCR_G2_IO3; /* (5) */ TSC->IOGCSR |= TSC_IOGCSR_G2E; /* (6) */ A.10.2 TSC interrupt code example /* End of acquisition flag */ if((TSC->ISR &...
Page 996 Code examples RM0367 /* (2) Enable the counter by writing CEN=1 in the TIMx_CR1 register. */ TIMx->SMCR TIM_SMCR_ETPS_0 | TIM_SMCR_ECE; /* (1) */ TIMx->CR1 |= TIM_CR1_CEN; /* (2) */ A.11.3 Input capture configuration code example /* (1) Select the active input TI1 (CC1S = 01), program the input filter for 8 clock cycles (IC1F = 0011), select the rising edge on CC1 (CC1P = 0, reset value) and prescaler at each valid transition (IC1PS = 00, reset value) */...
Page 997 RM0367 Code examples Counter counter1 0xFFFF counter0 + 1; counter0 = counter1; else /* Manage error */ Note: This code manages only single counter overflows. To manage several counter overflows, the update interrupt must be enabled (UIE = 1) and properly managed.
Page 998 Code examples RM0367 RCC->AHBENR |= RCC_AHBENR_DMA1EN; /* (1) */ DMA1_CSELR->CSELR /* (2) */ << * (5-1)) | << * (7-1)); DMA1_Channel5->CPAR = (uint32_t) (&(TIMx->CCR1)); /* (3) */ DMA1_Channel5->CMAR = (uint32_t)(&Period); /* (4) */ DMA1_Channel5->CNDTR = 1; /* (5) */ DMA1_Channel5->CCR DMA_CCR_MSIZE_0 DMA_CCR_PSIZE_0 \ DMA_CCR_TEIE...
Page 999 RM0367 Code examples /* (4) Select PWM mode 1 on OC1 (OC1M = 110), enable preload register on OC1 (OC1PE = 1) */ /* (5) Select active high polarity on OC1 (CC1P = 0, reset value), enable the output on OC1 (CC1E = 1) */ /* (6) Enable output (MOE = 1)- optional*/ /* (7) Enable counter (CEN = 1) select edge aligned mode (CMS = 00, reset value)
Page 1000 Code examples RM0367 enable preload register on OC1 (OC1PE = 1) enable clearing on OC1 for ETR clearing (OC1CE = 1)*/ /* (5) Select active high polarity on OC1 (CC1P = 0, reset value), enable the output on OC1 (CC1E = 1)*/ /* (6) Select ETR as OCREF clear source (reserved bit = 1) select External Trigger Prescaler off (ETPS = 00, reset value) disable external clock mode 2 (ECE = 0, reset value)