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RM0351
30.7.8
LPTIM counter register (LPTIMx_CNT)
Address offset: 0x1C
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 CNT: Counter value
When the LPTIM is running with an asynchronous clock, reading the LPTIMx_CNT register may
return unreliable values. So in this case it is necessary to perform two consecutive read accesses
and verify that the two returned values are identical.
It should be noted that for a reliable LPTIM_CNT register read access, two consecutive read
accesses must be performed and compared. A read access can be considered reliable when the
values of the two consecutive read accesses are equal.
30.7.9
LPTIM1 option register (LPTIM1_OR)
Address offset: 0x20
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 OR_1: Option register bit 1
0:
LPTIM1 input 2 is connected to I/O
1:
LPTIM1 input 2 is connected to COMP2_OUT
Bit 0 OR_0: Option register bit 0
0:
LPTIM1 input 1 is connected to I/O
1:
LPTIM1 input 1 is connected to COMP1_OUT
30.7.10
LPTIM2 option register (LPTIM2_OR)
Address offset: 0x20
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
27
26
25
24
Res.
Res.
Res.
Res.
DocID024597 Rev 3
23
22
21
Res.
Res.
Res.
7
6
5
CNT[15:0]
r
23
22
21
Res.
Res.
Res.
7
6
5
Res.
Res.
Res.
23
22
21
Res.
Res.
Res.
Low-power timer (LPTIM)
20
19
18
17
Res.
Res.
Res.
Res.
4
3
2
1
20
19
18
17
Res.
Res.
Res.
Res.
4
3
2
1
Res.
Res.
Res.
OR_1
rw
20
19
18
17
Res.
Res.
Res.
Res.
16
Res.
0
16
Res.
0
OR_0
rw
16
Res.
1043/1693
1045
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