ST STM32L4x6 Reference Manual page 790

Advanced-control timers (TIM1/TIM8)
The output enable signal and output levels during break are depending on several control
bits:
–
–
–
When exiting from reset, the break circuit is disabled and the MOE bit is low. You can enable
the break functions by setting the BKE and BKE2 bits in the TIMx_BDTR register. The break
input polarities can be selected by configuring the BKP and BKP2 bits in the same register.
BKEx and BKPx can be modified at the same time. When the BKEx and BKPx bits are
written, a delay of 1 APB clock cycle is applied before the writing is effective. Consequently,
it is necessary to wait 1 APB clock period to correctly read back the bit after the write
operation.
Because MOE falling edge can be asynchronous, a resynchronization circuit has been
inserted between the actual signal (acting on the outputs) and the synchronous control bit
(accessed in the TIMx_BDTR register). It results in some delays between the asynchronous
and the synchronous signals. In particular, if you write MOE to 1 whereas it was low, you
must insert a delay (dummy instruction) before reading it correctly. This is because you write
the asynchronous signal and read the synchronous signal.
The break can be generated from multiple sources which can be individually enabled and
with programmable edge sensitivity, using the TIMx_OR2 and TIMx_OR3 registers.
The source for break (BRK) channel is:
•
An external source connected to one of the BKIN pin (as per selection done in the
AFIO controller), with polarity selection and optional digital filtering
•
An internal source:
–
–
–
–
–
–
–
The source for break2 (BRK2) can be:
• An external source connected to one of the BKIN pin (as per selection done in the
AFIO controller), with polarity selection and optional digital filtering
•
An internal source coming from a comparator output.
Break events can also be generated by software using BG and B2G bits in the TIMx_EGR
register.
790/1693
the MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
software and is reset in case of break or break2 event.
the OSSI bit in the TIMx_BDTR register defines whether the timer controls the
output in inactive state or releases the control to the GPIO controller (typically to
have it in Hi-Z mode)
the OISx and OISxN bits in the TIMx_CR2 register which are setting the output
shut-down level, either active or inactive. The OCx and OCxN outputs cannot be
set both to active level at a given time, whatever the OISx and OISxN values.
Refer to Table 149: Output control bits for complementary OCx and OCxN
channels with break feature on page 832
®
the Cortex -M4 LOCKUP output
the PVD output
the SRAM parity error signal
a flash ECC error
a clock failure event generated by the CSS detector
the output from a comparator, with polarity selection and optional digital filtering
the analog watchdog output of the DFSDM peripheral
DocID024597 Rev 3
for more details.
RM0351