ST STM32F100 Series Manuals

Manuals and User Guides for ST STM32F100 Series. We have 3 ST STM32F100 Series manuals available for free PDF download: Reference Manual, Application Note

ST STM32F100 Series Reference Manual (709 pages)

Advanced Arm-based 32-bit MCUs

Brand: ST | Category: Microcontrollers | Size: 8.5 MB

Table of Contents
2
Documentation Conventions
32
List of Abbreviations for Registers
32
Glossary
32
Peripheral Availability
32
General Information
33
Memory and Bus Architecture
34
System Architecture
34
Figure 1. Low and Medium Density Value Line System Architecture
34
Figure 2. High Density Value Line System Architecture
35
Memory Organization
36
Memory Map
37
Table 1. Low and Medium-Density Device Register Boundary Addresses
37
Table 2. High-Density Device Register Boundary Addresses
38
Embedded SRAM
40
Bit Banding
41
Embedded Flash Memory
41
Table 3. Flash Module Organization (Low-Density Value Line Devices)
42
Table 4. Flash Module Organization (Medium-Density Value Line Devices)
43
Table 5. Flash Module Organization (High-Density Value Line Devices)
44
Boot Configuration
45
Table 6. Boot Modes
45
CRC Calculation Unit
47
CRC Introduction
47
CRC Main Features
47
Figure 3. CRC Calculation Unit Block Diagram
47
CRC Functional Description
48
CRC Registers
48
Data Register (CRC_DR)
48
Independent Data Register (CRC_IDR)
48
Control Register (CRC_CR)
49
CRC Register Map
49
Table 7. CRC Calculation Unit Register Map and Reset Values
49
Power Control (PWR)
50
Power Supplies
50
Figure 4. Power Supply Overview
50
Independent A/D and D/A Converter Supply and Reference Voltage
51
Battery Backup Domain
51
Voltage Regulator
52
Power Supply Supervisor
52
Power on Reset (Por)/Power down Reset (PDR)
52
Programmable Voltage Detector (PVD)
53
Figure 5. Power on Reset/Power down Reset Waveform
53
Figure 6. PVD Thresholds
54
Low-Power Modes
55
Slowing down System Clocks
55
Table 8. Low-Power Mode Summary
55
Peripheral Clock Gating
56
Sleep Mode
56
Stop Mode
57
Table 9. Sleep-Now
57
Table 10. Sleep-On-Exit
57
Table 11. Stop Mode
58
Standby Mode
59
Table 12. Standby Mode
59
Auto-Wakeup (AWU) from Low-Power Mode
60
Power Control Registers
60
Power Control Register (PWR_CR)
60
Power Control/Status Register (PWR_CSR)
62
PWR Register Map
63
Table 13. PWR Register Map and Reset Values
63
Backup Registers (BKP)
64
BKP Introduction
64
BKP Main Features
64
BKP Functional Description
65
Tamper Detection
65
RTC Calibration
65
BKP Registers
66
Backup Data Register X (Bkp_Drx) (X = 1
66
RTC Clock Calibration Register (BKP_RTCCR)
66
Backup Control Register (BKP_CR)
67
Backup Control/Status Register (BKP_CSR)
67
BKP Register Map
69
Table 14. BKP Register Map and Reset Values
69
Reset and Clock Control (RCC)
71
Reset
71
System Reset
71
Power Reset
72
Backup Domain Reset
72
Clocks
72
Figure 7. Simplified Diagram of the Reset Circuit
72
Figure 8. Stm32F100Xx Clock Tree (Low and Medium-Density Devices)
73
Figure 9. Stm32F100Xx Clock Tree (High-Density Devices)
74
HSE Clock
75
Figure 10. HSE/ LSE Clock Sources
75
HSI Clock
76
Pll
76
LSE Clock
77
LSI Clock
77
System Clock (SYSCLK) Selection
78
Clock Security System (CSS)
78
RTC Clock
78
Watchdog Clock
79
Clock-Out Capability
79
RCC Registers
80
Clock Control Register (RCC_CR)
80
Clock Configuration Register (RCC_CFGR)
82
Clock Interrupt Register (RCC_CIR)
84
APB2 Peripheral Reset Register (RCC_APB2RSTR)
86
APB1 Peripheral Reset Register (RCC_APB1RSTR)
88
AHB Peripheral Clock Enable Register (RCC_AHBENR)
90
APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
92
APB1 Peripheral Clock Enable Register (RCC_APB1ENR)
94
Backup Domain Control Register (RCC_BDCR)
97
Control/Status Register (RCC_CSR)
98
Clock Configuration Register2 (RCC_CFGR2)
100
RCC Register Map
101
Table 15. RCC Register Map and Reset Values
101
General-Purpose and Alternate-Function I/Os
102
(Gpios and Afios)
102
GPIO Functional Description
102
Figure 11. Basic Structure of a Standard I/O Port Bit
103
Figure 12. Basic Structure of a 5-Volt Tolerant I/O Port Bit
103
General-Purpose I/O (GPIO)
104
Atomic Bit Set or Reset
104
Table 16. Port Bit Configuration Table
104
Table 17. Output MODE Bits
104
External Interrupt/Wakeup Lines
105
Alternate Functions (AF)
105
Software Remapping of I/O Alternate Functions
105
GPIO Locking Mechanism
105
Input Configuration
106
Output Configuration
106
Figure 13. Input Floating/Pull Up/Pull down Configurations
106
Alternate Function Configuration
107
Figure 14. Output Configuration
107
Analog Configuration
108
Figure 15. Alternate Function Configuration
108
GPIO Configurations for Device Peripherals
109
Table 18. Advanced Timer TIM1
109
Table 19. General-Purpose Timers TIM2/3/4/5
109
Table 20. General-Purpose Timers TIM15/16/17
109
Figure 16. High Impedance-Analog Configuration
109
Table 21. General-Purpose Timers TIM12/13/14
110
Table 22. Usarts
110
Table 23. SPI
110
Table 24. CEC
111
Table 25. I2C
111
Table 26. FSMC
111
Figure 17. ADC / DAC
111
Table 27. Other Ios
112
GPIO Registers
113
Port Configuration Register Low (Gpiox_Crl) (X=A..g
113
Port Configuration Register High (Gpiox_Crh) (X=A..g
114
Port Input Data Register (Gpiox_Idr) (X=A..g
114
Port Output Data Register (Gpiox_Odr) (X=A
115
Port Bit Set/Reset Register (Gpiox_Bsrr) (X=A
115
Port Bit Reset Register (Gpiox_Brr) (X=A..g
116
Port Configuration Lock Register (Gpiox_Lckr) (X=A..g
116
Alternate Function I/O and Debug Configuration (AFIO)
117
Using OSC32_IN/OSC32_OUT Pins as GPIO Ports PC14/PC15
117
Using OSC_IN/OSC_OUT Pins as GPIO Ports PD0/PD1
117
JTAG/SWD Alternate Function Remapping
118
Timer Alternate Function Remapping
118
Table 28. Debug Interface Signals
118
Table 29. Debug Port Mapping
118
Table 30. TIM5 Alternate Function Remapping
119
Table 31. TIM12 Remapping
119
Table 32. TIM13 Remapping
119
Table 33. TIM14 Remapping
119
Table 34. TIM4 Alternate Function Remapping
119
Table 35. TIM3 Alternate Function Remapping
119
Table 36. TIM2 Alternate Function Remapping
120
Table 37. TIM1 Alternate Function Remapping
120
Table 38. TIM1 DMA Remapping
120
Table 39. TIM15 Remapping
120
USART Alternate Function Remapping
121
Table 40. TIM16 Remapping
121
Table 41. TIM17 Remapping
121
Table 42. USART3 Remapping
121
Table 43. USART2 Remapping
121
Table 44. USART1 Remapping
121
I2C1 Alternate Function Remapping
122
SPI1 Alternate Function Remapping
122
CEC Remap
122
Table 45. I2C1 Remapping
122
Table 46. SPI1 Remapping
122
Table 47. CEC Remapping
122
AFIO Registers
123
Event Control Register (AFIO_EVCR)
123
AF Remap and Debug I/O Configuration Register (AFIO_MAPR)
124
External Interrupt Configuration Register 1 (AFIO_EXTICR1)
126
External Interrupt Configuration Register 2 (AFIO_EXTICR2)
126
External Interrupt Configuration Register 3 (AFIO_EXTICR3)
127
External Interrupt Configuration Register 4 (AFIO_EXTICR4)
127
AF Remap and Debug I/O Configuration Register (AFIO_MAPR2)
128
GPIO and AFIO Register Maps
130
Table 48. GPIO Register Map and Reset Values
130
Table 49. AFIO Register Map and Reset Values
130
Interrupts and Events
132
Nested Vectored Interrupt Controller (NVIC)
132
Systick Calibration Value Register
132
Interrupt and Exception Vectors
132
Table 50. Vector Table for Stm32F100Xx Devices
132
External Interrupt/Event Controller (EXTI)
136
Main Features
136
Block Diagram
136
Figure 18. External Interrupt/Event Controller Block Diagram
136
Wakeup Event Management
137
Functional Description
137
External Interrupt/Event Line Mapping
138
Figure 19. External Interrupt/Event GPIO Mapping
139
EXTI Registers
140
Interrupt Mask Register (EXTI_IMR)
140
Event Mask Register (EXTI_EMR)
140
Rising Trigger Selection Register (EXTI_RTSR)
141
Falling Trigger Selection Register (EXTI_FTSR)
141
Software Interrupt Event Register (EXTI_SWIER)
142
Pending Register (EXTI_PR)
142
EXTI Register Map
143
Table 51. External Interrupt/Event Controller Register Map and Reset Values
143
Direct Memory Access Controller (DMA)
144
DMA Introduction
144
DMA Main Features
144
Figure 20. DMA Block Diagram in Low and Medium- Density
145
DMA Functional Description
146
DMA Transactions
146
Figure 21. DMA Block Diagram in High-Density Cat.4 and Cat.5 Stm32F100Xx Devices
146
Arbiter
147
DMA Channels
147
Programmable Data Width, Data Alignment and Endians
149
Table 52. Programmable Data Width and Endian Behavior (When Bits PINC = MINC = 1)
149
Error Management
150
Interrupts
150
DMA Request Mapping
150
Table 53. DMA Interrupt Requests
150
Figure 22. DMA1 Request Mapping
151
Table 54. Summary of DMA1 Requests for each Channel
152
Table 55. Summary of DMA2 Requests for each Channel
153
Figure 23. DMA2 Request Mapping
153
DMA Registers
154
DMA Interrupt Status Register (DMA_ISR)
154
DMA Interrupt Flag Clear Register (DMA
155
DMA Channel X Configuration Register (Dma_Ccrx) (X = 1
156
DMA Channel X Number of Data Register (Dma_Cndtrx) (X = 1
157
DMA Channel X Peripheral Address Register (Dma_Cparx) (X = 1
158
DMA Channel X Memory Address Register (Dma_Cmarx) (X = 1
158
DMA Register Map
159
Table 56. DMA Register Map and Reset Values
159
Analog-To-Digital Converter (ADC)
162
ADC Introduction
162
ADC Main Features
162
ADC Functional Description
163
Figure 24. Single ADC Block Diagram
163
ADC On-Off Control
164
ADC Clock
164
Channel Selection
164
Table 57. ADC Pins
164
Single Conversion Mode
165
Continuous Conversion Mode
165
Timing Diagram
165
Analog Watchdog
166
Table 58. Analog Watchdog Channel Selection
166
Figure 25. Timing Diagram
166
Figure 26. Analog Watchdog Guarded Area
166
Scan Mode
167
Injected Channel Management
167
Discontinuous Mode
168
Figure 27. Injected Conversion Latency
168
Calibration
169
Data Alignment
170
Figure 28. Calibration Timing Diagram
170
Figure 29. Right Alignment of Data
170
Figure 30. Left Alignment of Data
170
Channel-By-Channel Programmable Sample Time
171
Conversion on External Trigger
171
Table 59. External Trigger for Regular Channels for ADC1
171
Table 60. External Trigger for Injected Channels for ADC1
171
DMA Request
172
Temperature Sensor
172
Figure 31. Temperature Sensor and VREFINT Channel Block Diagram
173
ADC Interrupts
174
Table 61. ADC Interrupts
174
ADC Registers
175
ADC Status Register (ADC_SR)
175
ADC Control Register 1 (ADC_CR1)
176
ADC Control Register 2 (ADC_CR2)
177
ADC Sample Time Register 1 (ADC_SMPR1)
180
ADC Sample Time Register 2 (ADC_SMPR2)
181
ADC Injected Channel Data Offset Register X (Adc_Jofrx) (X=1
181
ADC Watchdog High Threshold Register (ADC_HTR)
182
ADC Watchdog Low Threshold Register (ADC_LTR)
182
ADC Regular Sequence Register 1 (ADC_SQR1)
183
ADC Regular Sequence Register 2 (ADC_SQR2)
184
ADC Regular Sequence Register 3 (ADC_SQR3)
185
ADC Injected Sequence Register (ADC_JSQR)
186
ADC Injected Data Register X (Adc_Jdrx) (X= 1
187
ADC Regular Data Register (ADC_DR)
187
10.11.15 ADC Register Map
188
Table 62. ADC Register Map and Reset Values
188
Digital-To-Analog Converter (DAC)
190
DAC Introduction
190
DAC Main Features
190
Table 63. DAC Pins
191
Figure 32. DAC Channel Block Diagram
191
DAC Functional Description
192
DAC Channel Enable
192
DAC Output Buffer Enable
192
DAC Data Format
192
DAC Conversion
193
Figure 33. Data Registers in Single DAC Channel Mode
193
Figure 34. Data Registers in Dual DAC Channel Mode
193
DAC Output Voltage
194
DAC Trigger Selection
194
Table 64. External Triggers
194
Figure 35. Timing Diagram for Conversion with Trigger Disabled TEN = 0
194
DMA Request
195
Noise Generation
195
Triangle-Wave Generation
196
Figure 36. DAC LFSR Register Calculation Algorithm
196
Figure 37. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation
196
Dual DAC Channel Conversion
197
Figure 38. DAC Triangle Wave Generation
197
Figure 39. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation
197
Independent Trigger Without Wave Generation
198
Independent Trigger with Single LFSR Generation
198
Independent Trigger with Different LFSR Generation
198
Independent Trigger with Single Triangle Generation
199
Independent Trigger with Different Triangle Generation
199
Simultaneous Software Start
199
Load the Dual DAC Channel Data into the Desired DHR Register
199
DAC_DHR12LD or DAC_DHR8RD)
199
Simultaneous Trigger Without Wave Generation
200
Simultaneous Trigger with Single LFSR Generation
200
Simultaneous Trigger with Different LFSR Generation
200
Value in the Mampx[3:0] Bits
200
Set the Two DAC Channel Trigger Enable Bits TEN1 and TEN2
200
Load the Dual DAC Channel Data into the Desired DHR Register
200
Simultaneous Trigger with Single Triangle Generation
201
Simultaneous Trigger with Different Triangle Generation
201
DAC_DHR12LD or DAC_DHR8RD)
201
MAMP2[3:0], Is Added to the DHR2 Register and the Sum Is Transferred into DAC_DOR2
201
DAC Registers
202
DAC Control Register (DAC_CR)
202
DAC Software Trigger Register (DAC_SWTRIGR)
205
DAC Channel1 12-Bit Right-Aligned Data Holding Register (DAC_DHR12R1)
205
DAC Channel1 12-Bit Left Aligned Data Holding Register
206
(Dac_Dhr12L1)
206
DAC Channel1 8-Bit Right Aligned Data Holding Register
206
DAC Channel2 12-Bit Right Aligned Data Holding Register
207
DAC Channel2 12-Bit Left Aligned Data Holding Register
207
(Dac_Dhr12L2)
207
DAC Channel2 8-Bit Right-Aligned Data Holding Register
207
Dual DAC 12-Bit Right-Aligned Data Holding Register (DAC_DHR12RD)
208
DUAL DAC 12-Bit Left Aligned Data Holding Register
208
(Dac_Dhr12Ld)
208
DUAL DAC 8-Bit Right Aligned Data Holding Register
209
DAC Channel1 Data Output Register (DAC_DOR1)
209
DAC Channel2 Data Output Register (DAC_DOR2)
209
DAC Status Register (DAC_SR)
210
DAC Register Map
210
Table 65. DAC Register Map
210
Advanced-Control Timer (TIM1)
212
TIM1 Introduction
212
TIM1 Main Features
213
Figure 40. Advanced-Control Timer Block Diagram
214
TIM1 Functional Description
215
Time-Base Unit
215
Figure 41. Counter Timing Diagram with Prescaler Division Change from 1 to 2
216
Figure 42. Counter Timing Diagram with Prescaler Division Change from 1 to 4
216
Counter Modes
217
Figure 43. Counter Timing Diagram, Internal Clock Divided by 1
217
Figure 44. Counter Timing Diagram, Internal Clock Divided by 2
218
Figure 45. Counter Timing Diagram, Internal Clock Divided by 4
218
Figure 46. Counter Timing Diagram, Internal Clock Divided by N
218
Figure 47. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
219
Figure 48. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
219
Figure 49. Counter Timing Diagram, Internal Clock Divided by 1
221
Figure 50. Counter Timing Diagram, Internal Clock Divided by 2
221
Figure 51. Counter Timing Diagram, Internal Clock Divided by 4
222
Figure 52. Counter Timing Diagram, Internal Clock Divided by N
222
Figure 53. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
223
Figure 54. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr = 0X6
224
Figure 55. Counter Timing Diagram, Internal Clock Divided by 2
224
Figure 56. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
225
Figure 57. Counter Timing Diagram, Internal Clock Divided by N
225
Repetition Counter
226
Figure 58. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
226
Figure 59. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
226
Figure 60. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
227
Clock Selection
228
Figure 61. Control Circuit in Normal Mode, Internal Clock Divided by 1
228
Figure 62. TI2 External Clock Connection Example
229
Figure 63. Control Circuit in External Clock Mode 1
230
Figure 64. External Trigger Input Block
230
Capture/Compare Channels
231
Figure 65. Control Circuit in External Clock Mode 2
231
Figure 66. Capture/Compare Channel (Example: Channel 1 Input Stage)
232
Figure 67. Capture/Compare Channel 1 Main Circuit
232
Figure 68. Output Stage of Capture/Compare Channel (Channel 1 to 3)
233
Figure 69. Output Stage of Capture/Compare Channel (Channel 4)
233
Input Capture Mode
234
PWM Input Mode
235
Forced Output Mode
235
Figure 70. PWM Input Mode Timing
235
Output Compare Mode
236
PWM Mode
237
Figure 71. Output Compare Mode, Toggle on OC1
237
Figure 72. Edge-Aligned PWM Waveforms (ARR=8)
238
Figure 73. Center-Aligned PWM Waveforms (ARR=8)
239
Complementary Outputs and Dead-Time Insertion
240
Figure 74. Complementary Output with Dead-Time Insertion
241
Figure 75. Dead-Time Waveforms with Delay Greater than the Negative Pulse
241
Figure 76. Dead-Time Waveforms with Delay Greater than the Positive Pulse
241
Using the Break Function
242
Figure 77. Output Behavior in Response to a Break
244
Clearing the Ocxref Signal on an External Event
245
Figure 78. Clearing Timx Ocxref
245
6-Step PWM Generation
246
Figure 79. 6-Step Generation, COM Example (OSSR=1)
246
One-Pulse Mode
247
Figure 80. Example of One Pulse Mode
247
Encoder Interface Mode
248
Table 66. Counting Direction Versus Encoder Signals
249
Figure 81. Example of Counter Operation in Encoder Interface Mode
250
Figure 82. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
250
Timer Input XOR Function
251
Interfacing with Hall Sensors
251
Figure 83. Example of Hall Sensor Interface
252
Timx and External Trigger Synchronization
253
Figure 84. Control Circuit in Reset Mode
253
Figure 85. Control Circuit in Gated Mode
254
Figure 86. Control Circuit in Trigger Mode
255
Timer Synchronization
256
Debug Mode
256
Figure 87. Control Circuit in External Clock Mode 2 + Trigger Mode
256
TIM1 Registers
257
TIM1 Control Register 1 (Timx_Cr1)
257
TIM1 Control Register 2 (Timx_Cr2)
258
TIM1 Slave Mode Control Register (Timx_Smcr)
261
TIM1 Dma/Interrupt Enable Register (Timx_Dier)
263
Table 67. Timx Internal Trigger Connection
263
TIM1 Status Register (Timx_Sr)
265
TIM1 Event Generation Register (Timx_Egr)
266
TIM1 Capture/Compare Mode Register 1 (Timx_Ccmr1)
268
TIM1 Capture/Compare Mode Register 2 (Timx_Ccmr2)
270
TIM1 Capture/Compare Enable Register (Timx_Ccer)
272
TIM1 Counter (Timx_Cnt)
274
TIM1 Prescaler (Timx_Psc)
274
Table 68. Output Control Bits for Complementary Ocx and Ocxn Channels with
274
Table 80. Output Control Bits for Complementary Ocx and Ocxn Channels with Break Feature
274
TIM1 Auto-Reload Register (Timx_Arr)
275
TIM1 Repetition Counter Register (Timx_Rcr)
276
TIM1 Capture/Compare Register 1 (Timx_Ccr1)
276
TIM1 Capture/Compare Register 2 (Timx_Ccr2)
277
TIM1 Capture/Compare Register 3 (Timx_Ccr3)
277
TIM1 Capture/Compare Register 4 (Timx_Ccr4)
278
TIM1 Break and Dead-Time Register (Timx_Bdtr)
278
TIM1 DMA Control Register (Timx_Dcr)
280
TIM1 DMA Address for Full Transfer (Timx_Dmar)
281
TIM1 Register Map
282
Table 69. TIM1 Register Map and Reset Values
282
General-Purpose Timers (TIM2 to TIM5)
284
TIM2 to TIM5 Introduction
284
TIM2 to TIM5 Main Features
285
TIM2 to TIM5 Functional Description
286
Time-Base Unit
286
Figure 88. General-Purpose Timer Block Diagram
286
Figure 89. Counter Timing Diagram with Prescaler Division Change from 1 to 2
287
Counter Modes
288
Figure 90. Counter Timing Diagram with Prescaler Division Change from 1 to 4
288
Figure 91. Counter Timing Diagram, Internal Clock Divided by 1
289
Figure 92. Counter Timing Diagram, Internal Clock Divided by 2
289
Figure 93. Counter Timing Diagram, Internal Clock Divided by 4
289
Figure 94. Counter Timing Diagram, Internal Clock Divided by N
290
Figure 95. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
290
Figure 96. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
291
Figure 97. Counter Timing Diagram, Internal Clock Divided by 1
292
Figure 98. Counter Timing Diagram, Internal Clock Divided by 2
292
Figure 99. Counter Timing Diagram, Internal Clock Divided by 4
292
Figure 100. Counter Timing Diagram, Internal Clock Divided by N
293
Figure 101. Counter Timing Diagram, Update Event
293
Figure 102. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6
294
Figure 103. Counter Timing Diagram, Internal Clock Divided by 2
295
Figure 104. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
295
Figure 105. Counter Timing Diagram, Internal Clock Divided by N
295
Figure 106. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
296
Figure 107. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
296
Clock Selection
297
Figure 108. Control Circuit in Normal Mode, Internal Clock Divided by 1
297
Figure 109. TI2 External Clock Connection Example
298
Figure 110. Control Circuit in External Clock Mode 1
299
Figure 111. External Trigger Input Block
299
Capture/Compare Channels
300
Figure 112. Control Circuit in External Clock Mode 2
300
Figure 113. Capture/Compare Channel (Example: Channel 1 Input Stage)
300
Figure 114. Capture/Compare Channel 1 Main Circuit
301
Figure 115. Output Stage of Capture/Compare Channel (Channel 1)
301
Input Capture Mode
302
PWM Input Mode
303
Figure 116. PWM Input Mode Timing
303
Forced Output Mode
304
Output Compare Mode
304
PWM Mode
305
Figure 117. Output Compare Mode, Toggle on OC1
305
Figure 118. Edge-Aligned PWM Waveforms (ARR=8)
306
Figure 119. Center-Aligned PWM Waveforms (ARR=8)
307
One-Pulse Mode
308
Figure 120. Example of One-Pulse Mode
308
Clearing the Ocxref Signal on an External Event
309
Encoder Interface Mode
310
Figure 121. Clearing Timx Ocxref
310
Table 70. Counting Direction Versus Encoder Signals
311
Figure 122. Example of Counter Operation in Encoder Interface Mode
312
Figure 123. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
312
Timer Input XOR Function
313
Timers and External Trigger Synchronization
313
Figure 124. Control Circuit in Reset Mode
313
Figure 125. Control Circuit in Gated Mode
314
Figure 126. Control Circuit in Trigger Mode
315
Timer Synchronization
316
Figure 127. Control Circuit in External Clock Mode 2 + Trigger Mode
316
Figure 128. Master/Slave Timer Example
316
Figure 129. Gating TIM2 with OC1REF of TIM3
317
Figure 130. Gating TIM2 with Enable of TIM3
318
Figure 131. Triggering TIM2 with Update of TIM3
319
Figure 132. Triggering TIM2 with Enable of TIM3
319
Debug Mode
320
Figure 133. Triggering TIM3 and TIM2 with TIM3 TI1 Input
320
Timx2 to TIM5 Registers
321
Timx Control Register 1 (Timx_Cr1)
321
Timx Control Register 2 (Timx_Cr2)
323
Timx Slave Mode Control Register (Timx_Smcr)
324
Timx Dma/Interrupt Enable Register (Timx_Dier)
326
Table 71. Timx Internal Trigger Connection
326
Timx Status Register (Timx_Sr)
327
Timx Event Generation Register (Timx_Egr)
329
Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
330
Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
333
Timx Capture/Compare Enable Register (Timx_Ccer)
334
Timx Counter (Timx_Cnt)
335
Timx Prescaler (Timx_Psc)
335
Table 72. Output Control Bit for Standard Ocx Channels
335
Timx Auto-Reload Register (Timx_Arr)
336
Timx Capture/Compare Register 1 (Timx_Ccr1)
336
Timx Capture/Compare Register 2 (Timx_Ccr2)
337
Timx Capture/Compare Register 3 (Timx_Ccr3)
337
Timx Capture/Compare Register 4 (Timx_Ccr4)
337
Timx DMA Control Register (Timx_Dcr)
338
Timx DMA Address for Full Transfer (Timx_Dmar)
338
Timx Register Map
340
Table 73. Timx Register Map and Reset Values
340
General-Purpose Timers (TIM12/13/14)
342
TIM12/13/14 Introduction
342
TIM12/13/14 Main Features
342
TIM12 Main Features
342
TIM13/TIM14 Main Features
343
Figure 134. General-Purpose Timer Block Diagram (TIM12)
343
Figure 135. General-Purpose Timer Block Diagram (TIM13/14)
344
TIM12/13/14 Functional Description
345
Time-Base Unit
345
Figure 136. Counter Timing Diagram with Prescaler Division Change from 1 to 2
346
Figure 137. Counter Timing Diagram with Prescaler Division Change from 1 to 4
346
Counter Modes
347
Figure 138. Counter Timing Diagram, Internal Clock Divided by 1
347
Figure 139. Counter Timing Diagram, Internal Clock Divided by 2
348
Figure 140. Counter Timing Diagram, Internal Clock Divided by 4
348
Figure 141. Counter Timing Diagram, Internal Clock Divided by N
348
Figure 142. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
349
Figure 143. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
349
Clock Selection
350
Figure 144. Control Circuit in Normal Mode, Internal Clock Divided by 1
350
Figure 145. TI2 External Clock Connection Example
351
Figure 146. Control Circuit in External Clock Mode 1
351
Capture/Compare Channels
352
Figure 147. Capture/Compare Channel (Example: Channel 1 Input Stage)
352
Input Capture Mode
353
Figure 148. Capture/Compare Channel 1 Main Circuit
353
Figure 149. Output Stage of Capture/Compare Channel (Channel 1)
353
PWM Input Mode (Only for TIM12)
355
Figure 150. PWM Input Mode Timing
355
Forced Output Mode
356
Output Compare Mode
356
PWM Mode
357
Figure 151. Output Compare Mode, Toggle on OC1
357
One-Pulse Mode
358
Figure 152. Edge-Aligned PWM Waveforms (ARR=8)
358
Figure 153. Example of One Pulse Mode
359
TIM12 External Trigger Synchronization
360
Figure 154. Control Circuit in Reset Mode
361
Figure 155. Control Circuit in Gated Mode
362
Figure 156. Control Circuit in Trigger Mode
362
Timer Synchronization (TIM12)
363
Debug Mode
363
TIM12 Registers
364
TIM12 Control Register 1 (Timx_Cr1)
364
TIM12 Control Register 2 (Timx_Cr2)
365
TIM12 Slave Mode Control Register (Timx_Smcr)
366
TIM12 Interrupt Enable Register (Timx_Dier)
367
Table 74. Timx Internal Trigger Connection
367
TIM12 Status Register (Timx_Sr)
369
TIM Event Generation Register (Timx_Egr)
370
TIM Capture/Compare Mode Register 1 (Timx_Ccmr1)
371
TIM12 Capture/Compare Enable Register (Timx_Ccer)
374
TIM12 Counter (Timx_Cnt)
375
TIM12 Prescaler (Timx_Psc)
375
TIM12 Auto-Reload Register (Timx_Arr)
375
Table 75. Output Control Bit for Standard Ocx Channels
375
TIM12 Capture/Compare Register 1 (Timx_Ccr1)
376
TIM12 Capture/Compare Register 2 (Timx_Ccr2)
376
TIM12 Register Map
377
Table 76. TIM12 Register Map and Reset Values
377
TIM13/14 Registers
379
TIM13/14 Control Register 1 (Timx_Cr1)
379
TIM10/11/13/14 Interrupt Enable Register (Timx_Dier)
380
TIM13/14 Status Register (Timx_Sr)
380
TIM13/14 Event Generation Register (Timx_Egr)
381
TIM13/14 Capture/Compare Mode Register 1 (Timx_Ccmr1)
381
TIM13/14 Capture/Compare Enable Register (Timx_Ccer)
384
Table 77. Output Control Bit for Standard Ocx Channels
384
TIM13/14 Counter (Timx_Cnt)
385
TIM13/14 Prescaler (Timx_Psc)
385
TIM13/14 Auto-Reload Register (Timx_Arr)
385
TIM13/14 Capture/Compare Register 1 (Timx_Ccr1)
386
TIM13/14 Register Map
387
Table 78. TIM13/14 Register Map and Reset Values
387
General-Purpose Timers (TIM15/16/17)
388
TIM15/16/17 Introduction
388
TIM15 Main Features
389
TIM16 and TIM17 Main Features
390
Figure 157. TIM15 Block Diagram
391
Figure 158. TIM16 and TIM17 Block Diagram
392
TIM15/16/17 Functional Description
393
Time-Base Unit
393
Counter Modes
394
Figure 159. Counter Timing Diagram with Prescaler Division Change from 1 to 2
394
Figure 160. Counter Timing Diagram with Prescaler Division Change from 1 to 4
394
Figure 161. Counter Timing Diagram, Internal Clock Divided by 1
395
Figure 162. Counter Timing Diagram, Internal Clock Divided by 2
395
Figure 163. Counter Timing Diagram, Internal Clock Divided by 4
396
Figure 164. Counter Timing Diagram, Internal Clock Divided by N
396
Repetition Counter
397
Clock Selection
398
Figure 168. Control Circuit in Normal Mode, Internal Clock Divided by 1
399
Figure 169. TI2 External Clock Connection Example
399
Capture/Compare Channels
400
Figure 170. Control Circuit in External Clock Mode 1
400
Figure 171. Capture/Compare Channel (Example: Channel 1 Input Stage)
400
Figure 172. Capture/Compare Channel 1 Main Circuit
401
Figure 173. Output Stage of Capture/Compare Channel (Channel 1)
401
Figure 174. Output Stage of Capture/Compare Channel (Channel 2 for TIM15)
401
Input Capture Mode
402
PWM Input Mode (Only for TIM15)
403
Figure 175. PWM Input Mode Timing
403
Forced Output Mode
404
Output Compare Mode
404
PWM Mode
405
Figure 176. Output Compare Mode, Toggle on OC1
405
Figure 177. Edge-Aligned PWM Waveforms (ARR=8)
406
Complementary Outputs and Dead-Time Insertion
407
Figure 178. Complementary Output with Dead-Time Insertion
407
Figure 179. Dead-Time Waveforms with Delay Greater than the Negative Pulse
407
Using the Break Function
408
Figure 180. Dead-Time Waveforms with Delay Greater than the Positive Pulse
408
Figure 181. Output Behavior in Response to a Break
410
One-Pulse Mode
411
Figure 182. Example of One Pulse Mode
411
TIM15 and External Trigger Synchronization (Only for TIM15)
413
Figure 183. Control Circuit in Reset Mode
413
Figure 184. Control Circuit in Gated Mode
414
Timer Synchronization
415
Debug Mode
415
TIM15 Registers
415
Figure 185. Control Circuit in Trigger Mode
415
TIM15 Control Register 1 (TIM15_CR1)
416
TIM15 Control Register 2 (TIM15_CR2)
417
TIM15 Slave Mode Control Register (TIM15_SMCR)
418
Table 79. Timx Internal Trigger Connection
419
TIM15 Dma/Interrupt Enable Register (TIM15_DIER)
420
TIM15 Status Register (TIM15_SR)
421
TIM15 Event Generation Register (TIM15_EGR)
422
TIM15 Capture/Compare Mode Register 1 (TIM15_CCMR1)
423
TIM15 Capture/Compare Enable Register (TIM15_CCER)
426
TIM15 Counter (TIM15_CNT)
429
TIM15 Prescaler (TIM15_PSC)
429
TIM15 Auto-Reload Register (TIM15_ARR)
429
TIM15 Repetition Counter Register (TIM15_RCR)
430
TIM15 Capture/Compare Register 1 (TIM15_CCR1)
430
TIM15 Capture/Compare Register 2 (TIM15_CCR2)
431
TIM15 Break and Dead-Time Register (TIM15_BDTR)
431
TIM15 DMA Control Register (TIM15_DCR)
433
TIM15 DMA Address for Full Transfer (TIM15_DMAR)
434
TIM15 Register Map
434
Table 81. TIM15 Register Map and Reset Values
435
TIM16&TIM17 Registers
437
TIM16&TIM17 Control Register 1 (Timx_Cr1)
437
TIM16&TIM17 Control Register 2 (Timx_Cr2)
438
TIM16&TIM17 Dma/Interrupt Enable Register (Timx_Dier)
440
TIM16&TIM17 Status Register (Timx_Sr)
441
TIM16&TIM17 Event Generation Register (Timx_Egr)
442
TIM16&TIM17 Capture/Compare Mode Register 1 (Timx_Ccmr1)
443
TIM16&TIM17 Capture/Compare Enable Register (Timx_Ccer)
445
Table 82. Output Control Bits for Complementary Ocx and Ocxn Channels with Break Feature
447
TIM16&TIM17 Counter (Timx_Cnt)
448
TIM16&TIM17 Prescaler (Timx_Psc)
448
TIM16&TIM17 Auto-Reload Register (Timx_Arr)
448
TIM16&TIM17 Repetition Counter Register (Timx_Rcr)
449
TIM16&TIM17 Capture/Compare Register 1 (Timx_Ccr1)
449
TIM16&TIM17 Break and Dead-Time Register (Timx_Bdtr)
450
TIM16&TIM17 DMA Control Register (Timx_Dcr)
451
TIM16&TIM17 DMA Address for Full Transfer (Timx_Dmar)
452
TIM16&TIM17 Register Map
454
Table 83. TIM16&TIM17 Register Map and Reset Values
454
Basic Timers (TIM6 and TIM7)
456
TIM6 and TIM7 Introduction
456
TIM6 and TIM7 Main Features
456
TIM6 and TIM7 Functional Description
457
Time-Base Unit
457
Figure 186. Basic Timer Block Diagram
457
Figure 187. Counter Timing Diagram with Prescaler Division Change from 1 to 2
458
Counting Mode
459
Figure 188. Counter Timing Diagram with Prescaler Division Change from 1 to 4
459
Figure 189. Counter Timing Diagram, Internal Clock Divided by 1
460
Figure 190. Counter Timing Diagram, Internal Clock Divided by 2
460
Figure 191. Counter Timing Diagram, Internal Clock Divided by 4
461
Figure 192. Counter Timing Diagram, Internal Clock Divided by N
461
Clock Source
462
Figure 195. Control Circuit in Normal Mode, Internal Clock Divided by 1
462
Debug Mode
463
TIM6 and TIM7 Registers
463
TIM6 and TIM7 Control Register 1 (Timx_Cr1)
463
TIM6 and TIM7 Control Register 2 (Timx_Cr2)
465
TIM6 and TIM7 Dma/Interrupt Enable Register (Timx_Dier)
465
TIM6 and TIM7 Status Register (Timx_Sr)
466
TIM6 and TIM7 Event Generation Register (Timx_Egr)
466
TIM6 and TIM7 Counter (Timx_Cnt)
466
TIM6 and TIM7 Prescaler (Timx_Psc)
467
TIM6 and TIM7 Auto-Reload Register (Timx_Arr)
467
TIM6 and TIM7 Register Map
468
Table 84. TIM6 and TIM7 Register Map and Reset Values
468
Real-Time Clock (RTC)
469
RTC Introduction
469
RTC Main Features
470
RTC Functional Description
471
Overview
471
Figure 196. RTC Simplified Block Diagram
471
Resetting RTC Registers
472
Reading RTC Registers
472
Configuring RTC Registers
472
RTC Flag Assertion
473
Figure 197. RTC Second and Alarm Waveform Example with PR=0003, ALARM=00004
473
Figure 198. RTC Overflow Waveform Example with PR=0003
473
RTC Registers
474
RTC Control Register High (RTC_CRH)
474
RTC Control Register Low (RTC_CRL)
475
RTC Prescaler Load Register (RTC_PRLH / RTC_PRLL)
476
RTC Prescaler Divider Register (RTC_DIVH / RTC_DIVL)
477
RTC Counter Register (RTC_CNTH / RTC_CNTL)
478
RTC Alarm Register High (RTC_ALRH / RTC_ALRL)
479
RTC Register Map
480
Table 85. RTC Register Map and Reset Values
480
Independent Watchdog (IWDG)
481
IWDG Introduction
481
IWDG Main Features
481
IWDG Functional Description
481
Hardware Watchdog
482
Register Access Protection
482
Debug Mode
482
Table 86. Min/Max IWDG Timeout Period (in Ms) at 40 Khz (LSI)
482
Figure 199. Independent Watchdog Block Diagram
482
IWDG Registers
483
Key Register (IWDG_KR)
483
Prescaler Register (IWDG_PR)
483
Reload Register (IWDG_RLR)
484
Status Register (IWDG_SR)
484
IWDG Register Map
486
Table 87. IWDG Register Map and Reset Values
486
Window Watchdog (WWDG)
487
WWDG Introduction
487
WWDG Main Features
487
WWDG Functional Description
487
Figure 200. Watchdog Block Diagram
488
How to Program the Watchdog Timeout
489
Figure 201. Window Watchdog Timing Diagram
489
Debug Mode
490
Table 88. Minimum and Maximum Timeout Values @24 Mhz (F PCLK1 )
490
WWDG Registers
491
Control Register (WWDG_CR)
491
Configuration Register (WWDG_CFR)
492
Status Register (WWDG_SR)
492
WWDG Register Map
493
Table 89. WWDG Register Map and Reset Values
493
Flexible Static Memory Controller (FSMC)
494
FSMC Main Features
494
Block Diagram
495
AHB Interface
495
Figure 202. FSMC Block Diagram
495
Supported Memories and Transactions
496
External Device Address Mapping
497
NOR/PSRAM Address Mapping
497
Table 90. NOR/PSRAM Bank Selection
497
Table 91. External Memory Address
497
Figure 203. FSMC Memory Banks
497
NOR Flash/Psram Controller
498
Table 92. Programmable NOR/PSRAM Access Parameters
498
External Memory Interface Signals
499
Table 93. Nonmultiplexed I/O nor Flash
499
Table 94. Multiplexed I/O nor Flash
499
Table 95. Nonmultiplexed I/Os PSRAM/SRAM
500
Table 96. Multiplexed I/O PSRAM
500
Supported Memories and Transactions
501
Table 97. nor Flash/Psram Controller: Example of Supported Memories and Transactions
501
General Timing Rules
502
NOR Flash/Psram Controller Asynchronous Transactions
502

ST STM32F100 Series Application Note (36 pages)

Brand: ST | Category: Microcontrollers | Size: 0.57 MB

Table of Contents
2
High-Definition Multimedia Interface, Consumer Electronics Control (HDMI-CEC)

7
Hardware Environment

18
Firmware Description

23
Value Line Evaluation Board CEC Demonstration

27

ST STM32F100 Series Application Note (29 pages)

Brand: ST | Category: Computer Hardware | Size: 0.63 MB

Table of Contents
2
General Information
6
Power Supplies
7
Introduction
7
Independent A/D Converter Supply and Reference Voltage
7
Figure 1. Power Supply Overview
7
Battery Backup
8
Voltage Regulator
8
Power Supply Schemes
8
Reset and Power Supply Supervisor
9
Power on Reset (POR) / Power down Reset (PDR)
9
Figure 2. Power Supply Scheme
9
Figure 3. Power on Reset/Power down Reset Waveform
9
Programmable Voltage Detector (PVD)
10
System Reset
10
Figure 4. PVD Thresholds
10
Figure 5. Simplified Diagram of the Reset Circuit
11
Clocks
12
HSE OSC Clock
12
Figure 6. External Clock
12
Figure 7. Crystal/Ceramic Resonators
12
External Source (HSE Bypass)
13
External Crystal/Ceramic Resonator (HSE Crystal)
13
LSE OSC Clock
14
External Source (LSE Bypass)
14
External Crystal/Ceramic Resonator (LSE Crystal)
14
Figure 8. External Clock
14
Figure 9. Crystal/Ceramic Resonators
14
Clock Security System (CSS)
15
Boot Configuration
16
Boot Mode Selection
16
Boot Pin Connection
16
Table 2. Boot Modes
16
Figure 10. Boot Mode Selection Implementation Example
16
Embedded Boot Loader Mode
17
Debug Management
18
Introduction
18
SWJ Debug Port (Serial Wire and JTAG)
18
Pinout and Debug Port Pins
18
SWJ Debug Port Pins
18
Figure 11. Host-To-Board Connection
18
Flexible SWJ-DP Pin Assignment
19
Table 3. Debug Port Pin Assignment
19
Table 4. SWJ I/O Pin Availability
19
Internal Pull-Up and Pull-Down Resistors on JTAG Pins
20
SWJ Debug Port Connection with Standard JTAG Connector
20
Figure 12. JTAG Connector Implementation
20
Recommendations
21
Printed Circuit Board
21
Component Position
21

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