ST STM32L4x6 Reference Manual page 846

Advanced-control timers (TIM1/TIM8)
Bit 10 BKCMP1P: BRK COMP1 input polarity
This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP
polarity bit.
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK
Bit 9 BKINP: BRK BKIN input polarity
This bit selects the BKIN alternate function input sensitivity. It must be programmed together
with the BKP polarity bit.
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK
Bit 8 BKDFBK0E: BRK DFSDM_BREAK[0] enable
This bit enables the DFSDM_BREAK[0] for the timer's BRK input. DFSDM_BREAK[0] output
is 'ORed' with the other BRK sources.
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK
Bits 7:3 Reserved, must be kept at reset value
Bit 2 BKCMP2E: BRK COMP2 enable
This bit enables the COMP2 for the timer's BRK input. COMP2 output is 'ORed' with the other
BRK sources.
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK
Bit 1 BKCMP1E: BRK COMP1 enable
This bit enables the COMP1 for the timer's BRK input. COMP1 output is 'ORed' with the other
BRK sources.
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK
Bit 0 BKINE: BRK BKIN input enable
This bit enables the BKIN alternate function input for the timer's BRK input. BKIN input is
'ORed' with the other BRK sources.
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK
Note: Refer to
overview.
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0: COMP1 input is active high
1: COMP1 input is active low
bits in TIMx_BDTR register).
0: BKIN input is active high
1: BKIN input is active low
bits in TIMx_BDTR register).
0: DFSDM_BREAK[0] input disabled
1: DFSDM_BREAK[0] input enabled
bits in TIMx_BDTR register).
0: COMP2 input disabled
1: COMP2 input enabled
bits in TIMx_BDTR register).
0: COMP1 input disabled
1: COMP1 input enabled
bits in TIMx_BDTR register).
0: BKIN input disabled
1: BKIN input enabled
bits in TIMx_BDTR register).
Figure 210: TIM1 ETR input circuitry and to
DocID024597 Rev 3
Figure 232: Break and Break2 circuitry
RM0351