Shutdown Mode - ST STM32L4x6 Reference Manual

RM0351
5.3.10

Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. It is based on the
deepsleep mode, with the voltage regulator disabled. The V
powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also
switched off.
SRAM1, SRAM2 and register contents are lost except for registers in the Backup domain.
The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this
mode, therefore the switch to Backup domain is not supported.
I/O states in Shutdown mode
In the Shutdown mode, the I/Os can be configured either with a pull-up (refer to
PWR_PUCRx registers (x=A,B,C,D,E,F,G,H), or with a pull-down (refer to PWR_PDCRx
registers (x=A,B,C,D,E,F,G,H)), or can be kept in analog state. However this configuration is
lost when exiting the Shutdown mode due to the power-on reset.
The RTC outputs on PC13 are functional in Shutdown mode. PC14 and PC15 used for LSE
are also functional. 5 wakeup pins (WKUPx, x=1,2...5) and the 3 RTC tampers are available.
Entering Shutdown mode
The Shutdown mode is entered according
SLEEPDEEP bit in the Cortex
Refer to
In Shutdown mode, the following features can be selected by programming individual
control bits:
•
real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain
control register (RCC_BDCR). Caution: in case of VDD power-down the RTC content
will be lost.
•
external 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup
domain control register (RCC_BDCR)
Exiting Shutdown mode
The Shutdown mode is exit according
occurs when exiting from Shutdown mode. All registers (except for the ones in the Backup
domain) are reset after wakeup from Shutdown.
Refer to
®
Table 28: Shutdown mode
Table 28: Shutdown mode
Entering low power
-M4 System Control register is set.
for details on how to enter Shutdown mode.
Section : Exiting low power
for more details on how to exit Shutdown mode.
DocID024597 Rev 3
Power control (PWR)
domain is consequently
CORE
mode, when the
mode. A power-on reset
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