Table 52. 16-Bit Multiplexed I/O Nor Flash Memory; Table 53. Non-Multiplexed I/Os Psram/Sram; Table 54. 16-Bit Multiplexed I/O Psram - ST STM32L4x6 Reference Manual

RM0351
NOR Flash memory, 16-bit multiplexed I/Os
FMC signal name
CLK
A[25:16]
AD[15:0]
NE[x]
NOE
NWE
NL(=NADV)
NWAIT
The maximum capacity is 512 Mbits.
PSRAM/SRAM, non-multiplexed I/Os
FMC signal name
CLK
A[25:0]
D[15:0]
NE[x]
NOE
NWE
NL(= NADV)
NWAIT
NBL[1:0]
The maximum capacity is 512 Mbits.
PSRAM, 16-bit multiplexed I/Os
FMC signal name I/O
CLK
A[25:16]
AD[15:0]

Table 52. 16-bit multiplexed I/O NOR Flash memory

I/O
O
O
16-bit multiplexed, bidirectional address/data bus (the 16-bit address
I/O
A[15:0] and data D[15:0] are multiplexed on the databus)
O
O
O
Latch enable (this signal is called address valid, NADV, by some NOR
O
I

Table 53. Non-multiplexed I/Os PSRAM/SRAM

I/O
O Clock (only for PSRAM synchronous access)
O
I/O
O Chip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM))
O
O
O Address valid only for PSRAM input (memory signal name: NADV)
I
O Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable)

Table 54. 16-Bit multiplexed I/O PSRAM

O
O
16-bit multiplexed, bidirectional address/data bus (the 16-bit address
I/O
A[15:0] and data D[15:0] are multiplexed on the databus)
DocID024597 Rev 3
Flexible static memory controller (FSMC)
Function
Clock (for synchronous access)
Address bus
Chip Select, x = 1..4
Output enable
Write enable
Flash devices)
NOR Flash wait input signal to the FMC
Function
Address bus
Data bidirectional bus
Output enable
Write enable
PSRAM wait input signal to the FMC
Function
Clock (for synchronous access)
Address bus
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