Error Code Correction (Ecc); Table 7. Flash Module - 256 Kb Dual Bank Organization - ST STM32L4x6 Reference Manual

RM0351
Flash area
Bank 1
Main memory
Bank 2
Bank 1
Bank 2
Information block Bank 1
Bank 1
Bank 2
1. For 256 KB devices, option DUALBANK=1
3.3.2

Error code correction (ECC)

Data in Flash memory are 72-bits words: 8 bits are added per double word (64 bits). The
ECC mechanism supports:
•
One error detection and correction
•
Two errors detection
When one error is detected and corrected, the flag ECCC (ECC correction) is set in
ECC register
When two errors are detected, a flag ECCD (ECC detection) is set in FLASH_ECCR
register. In this case, a NMI is generated.
When an ECC error is detected, the address of the failing double word and its associated
bank are saved in ADDR_ECC[20:0] and BK_ECC in the FLASH_ECCR register.
ADDR_ECC[2:0] are always cleared.

Table 7. Flash module - 256 KB dual bank organization

Flash memory addresses
0x0800 0000 - 0x0800 07FF
0x0800 0800 - 0x0800 0FFF
0x0800 1000 - 0x0800 17FF
0x0800 1800 - 0x0800 1FFF
0x0801 F800 - 0x0801 FFFF
0x0802 0000 - 0x0802 07FF
0x0802 0800 - 0x0802 0FFF
0x0802 1000 - 0x0802 17FF
0x0802 1800 - 0x0802 1FFF
0x0803 F800 - 0x0803 FFFF
0x1FFF 0000 - 0x1FFF 6FFF
0x1FFF 8000 - 0x1FFF EFFF
0x1FFF 7000 - 0x1FFF 73FF
0x1FFF 7800 - 0x1FFF 780F
0x1FFF F800 - 0x1FFF F80F
(FLASH_ECCR). If ECCCIE is set, an interrupt is generated.
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DocID024597 Rev 3
Embedded Flash memory (FLASH)
(1)
Size
(bytes)
2 K
2 K
2 K
2 K
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2 K
2 K Page 256
2 K Page 257
2 K Page 258
2 K Page 259
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2 K Page 319
28 K
System memory
28 K
1 K OTP area
16
Option bytes
16
Name
Page 0
Page 1
Page 2
Page 3
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Flash
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