Syscfg Sram2 Control And Status Register (Syscfg_Scsr) - ST STM32L4x6 Reference Manual

System configuration controller (SYSCFG)
Bits 6:4 EXTI13[2:0]: EXTI13 configuration bits
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 EXTI12[2:0]: EXTI12 configuration bits
Note: Some of the I/O pins mentioned in the above register may not be available on small
packages.
8.2.7

SYSCFG SRAM2 control and status register (SYSCFG_SCSR)

Address offset: 0x18
System reset value: 0x0000 0000
31 30 29
Res Res Res
15 14 13
Res Res Res
Bits 31:2 Reserved, must be kept at reset value
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These bits are written by software to select the source input for the EXTI13 external
interrupt.
000: PA[13] pin
001: PB[13] pin
010: PC[13] pin
011: PD[13] pin
100: PE[13] pin
101: PF[13] pin
110: PG[13] pin
111: Reserved
These bits are written by software to select the source input for the EXTI12 external
interrupt.
000: PA[12] pin
001: PB[12] pin
010: PC[12] pin
011: PD[12] pin
100: PE[12] pin
101: PF[12] pin
110: PG[12] pin
111: Reserved
28 27 26 25
Res Res Res Res
12 11 10 9
Res Res Res Res
Bit 1 SRAM2BSY: SRAM2 busy by erase operation
0: No SRAM2 erase operation is on going.
1: SRAM2 erase operation is on going.
Bit 0 SRAM2ER: SRAM2 Erase
Setting this bit starts a hardware SRAM2 erase operation. This bit is
automatically cleared at the end of the SRAM2 erase operation.
Note: This bit is write-protected: setting this bit is possible only after the correct
key sequence is written in the SYSCFG_SKR register.
24 23 22
Res Res Res
8 7 6
Res Res Res
DocID024597 Rev 3
21 20 19 18
Res Res Res Res
5 4 3 2
Res Res Res Res
RM0351
17 16
Res Res
1 0
SRAM2 SRAM2
BSY ER
r rw