ST STM32L4x6 Reference Manual page 219

RM0351
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 QSPIRST: Quad SPI memory interface reset
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 FMCRST: Flexible memory controller reset
Set and cleared by software.
0: No effect
1: Reset QUADSPI
Set and cleared by software.
0: No effect
1: Reset FMC
DocID024597 Rev 3
Reset and clock control (RCC)
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