ST STM32L4x6 Reference Manual page 207

RM0351
Bits 22:21 PLLSAI1Q[1:0]: SAI1PLL division factor for PLL48M2CLK (48 MHz clock)
Caution:
Bit 20 PLLSAI1QEN: SAI1PLL PLL48M2CLK output enable
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 PLLSAI1P: SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock).
Bit 16 PLLSAI1PEN: SAI1PLL PLLSAI1CLK output enable
Set and cleared by software to control the frequency of the SAI1PLL output clock
PLL48M2CLK. This output can be selected for USB, RNG, SDMMC (48 MHz clock). These
bits can be written only if SAI1PLL is disabled.
PLL48M2CLK output clock frequency = VCOSAI1 frequency / PLLQ with PLLQ = 2, 4, 6, or
8
00: PLLQ = 2
01: PLLQ = 4
10: PLLQ = 6
11: PLLQ = 8
The software has to set these bits correctly not to exceed 80 MHz on this
domain.
Set and reset by software to enable the PLL48M2CLK output of the SAI1PLL.
In order to save power, when the PLL48M2CLK output of the SAI1PLL is not used, the value
of PLLSAI1QEN should be 0.
0: PLL48M2CLK output disable
1: PLL48M2CLK output enable
Set and cleared by software to control the frequency of the SAI1PLL output clock
PLLSAI1CLK. This output can be selected for SAI1 or SAI2. These bits can be written only if
SAI1PLL is disabled.
PLLSAI1CLK output clock frequency = VCOSAI1 frequency / PLLSAI1P with PLLSAI1P =7,
or 17
0: PLLSAI1P = 7
1: PLLSAI1P = 17
Set and reset by software to enable the PLLSAI1CLK output of the SAI1PLL.
In order to save power, when the PLLSAI1CLK output of the SAI1PLL is not used, the value
of PLLSAI1PEN should be 0.
0: PLLSAI1CLK output disable
1: PLLSAI1CLK output enable
DocID024597 Rev 3
Reset and clock control (RCC)
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