Figure 44. Asynchronous Wait During A Read Access Waveforms - ST STM32L4x6 Reference Manual

Flexible static memory controller (FSMC)
1. The memory asserts the WAIT signal aligned to NOE/NWE which toggles:
2. The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):
if
then:
DATAST
otherwise
where max_wait_assertion_time is the maximum time taken by the memory to assert
the WAIT signal once NEx/NOE/NWE is low.
Figure 44
memory access phase after WAIT is released by the asynchronous memory (independently
of the above cases).
1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register.
370/1693
DATAST ≥
max_wait_assertion_time address_phase
(
≥ ( × )
4 HCLK max_wait_assertion_time
+
and show the number of HCLK clock cycles that are added to the
Figure 45

Figure 44. Asynchronous wait during a read access waveforms

DocID024597 Rev 3
( 4 × HCLK ) max_wait_assertion_time
+
>
≥ ×
DATAST 4 HCLK
hold_phase
+
address_phase hold_phase
– –
RM0351
)