Table 261. Trdt Values; Otg Reset Register (Otg_Grstctl) - ST STM32L4x6 Reference Manual

USB on-the-go full-speed (OTG_FS)
Bit 8 SRPCAP: SRP-capable
The application uses this bit to control the
operates as a non-SRP-capable
B-device, it cannot request the connected A-device (host) to activate V
session.
0: SRP capability is not enabled.
1: SRP capability is enabled.
Note: Accessible in both device and host modes.
Bit 7 Reserved, must be kept at reset value.
Bit 6 PHYSEL: Full Speed serial transceiver select
This bit is always 1 with read-only access.
Bits5:3 Reserved, must be kept at reset value.
Bits 2:0 TOCAL: FS timeout calibration
The number of PHY clocks that the application programs in this field is added to the full-
speed interpacket timeout duration in the core to account for any additional delays
introduced by the PHY. This can be required, because the delay introduced by the PHY in
generating the line state condition can vary from one PHY to another.
The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The
application must program this field based on the speed of enumeration. The number of bit
times added per PHY clock is 0.25 bit times.
43.15.5

OTG reset register (OTG_GRSTCTL)

Address offset: 0x10
Reset value: 0x8000 0000
The application uses this register to reset various hardware features inside the core.
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Table 261. TRDT values

AHB frequency range (MHz)
Min
14.2
15
16
17.2
18.5
20
21.8
24
27.5
32
DocID024597 Rev 3
OTG_FS
controller's SRP capabilities. If the core
Max
15
16
17.2
18.5
20
21.8
24
27.5
32
-
RM0351
and start a
BUS
TRDT minimum value
0xF
0xE
0xD
0xC
0xB
0xA
0x9
0x8
0x7
0x6