Swpmi Option Register (Swpmi_Or) - ST STM32L4x6 Reference Manual

RM0351
40.6.9

SWPMI Option register (SWPMI_OR)

Address offset: 0x24
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Bits 31:2 Reserved, must be kept at reset value
Bit 1 SWP_CLASS: SWP class selection
This bit is used to select the SWP class (refer to
activation).
0: Class C: SWPMI_IO uses directly VDD voltage to operate in class C.
This configuration must be selected when VDD is in the range [1.62 V to 1.98 V]
1: Class B: SWPMI_IO uses an internal voltage regulator to operate in class B.
This configuration must be selected when VDD is in the range [2.70 V to 3.30 V]
Bit 0 SWP_TBYP: SWP transceiver bypass
This bit is used to bypass the internal transceiver (SWPMI_IO), and connect an external
transceiver.
0: Internal transceiver is enabled. The external interface for SWPMI is SWPMI_IO
(SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are not available on GPIOs)
1: Internal transceiver is disabled. SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals
are available as alternate function on GPIOs. This configuration is selected to connect an
external transceiver
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
DocID024597 Rev 3
Single Wire Protocol Master Interface (SWPMI)
23 22 21 20
Res. Res. Res. Res.
7 6 5 4
Section 40.3.2: SWP initialization and
19 18 17 16
Res. Res. Res. Res.
3 2 1 0
SWP_ SWP_
CLASS TBYP
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