Table 259. Data Fifo (Dfifo) Access Register Map; Table 260. Power And Clock Gating Control And Status Registers; Otg_Fs Registers - ST STM32L4x6 Reference Manual

USB on-the-go full-speed (OTG_FS)
Data FIFO (DFIFO) access register map
These registers, available in both host and device modes, are used to read or write the FIFO
space for a specific endpoint or a channel, in a given direction. If a host channel is of type
IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the
FIFO can only be written on the channel.
Device IN Endpoint 0/Host OUT Channel 0: DFIFO Write Access
Device OUT Endpoint 0/Host IN Channel 0: DFIFO Read Access
Device IN Endpoint 1/Host OUT Channel 1: DFIFO Write Access
Device OUT Endpoint 1/Host IN Channel 1: DFIFO Read Access
...
Device IN Endpoint x
Device OUT Endpoint x
1. Where x is 5 in device mode and 11 in host mode.
Power and clock gating CSR map
There is a single register for power and clock gating. It is available in both host and device
modes.
Power and clock gating control register
Reserved
43.15

OTG_FS registers

These registers are available in both host and device modes, and do not need to be
reprogrammed when switching between these modes.
Bit values in the register descriptions are expressed in binary unless otherwise specified.
43.15.1 OTG control and status register (OTG_GOTGCTL)
Address offset: 0x000
Reset value: 0x0001 0000
The OTG_GOTGCTL register controls the behavior and reflects the status of the OTG
function of the core.
1522/1693

Table 259. Data FIFO (DFIFO) access register map

FIFO access register section
(1)
/Host OUT Channel x
(1)
/Host IN Channel x

Table 260. Power and clock gating control and status registers

Register name
DocID024597 Rev 3
(1)
: DFIFO Write Access
(1)
: DFIFO Read Access
Acronym Offset address: 0xE00–0xFFF
PCGCR 0xE00-0xE04
- 0xE05–0xFFF
RM0351
Address range Access
w
0x1000–0x1FFC
r
w
0x2000–0x2FFC
r
... ...
w
0xX000–0xXFFC
r