Figure 433. Master Full Duplex Communication In Packed Mode - ST STM32L4x6 Reference Manual

Serial peripheral interface (SPI)

Figure 433. Master full duplex communication in packed mode

Assumptions for master full duplex communication in packed mode example:
•
Data size = 5 bit
•
Read/write FIFO is performed mostly by 16-bit access
•
FRXTH=0
If DMA is used:
•
Number of Tx frames to be transacted by DMA is set to 3
•
Number of Rx frames to be transacted by DMA is set to 3
•
PSIZE for both Tx and Rx DMA channel is set to 16-bit
•
LDMA_TX=1 and LDMA_RX=1
See also
and notes.
1302/1685
: Communication diagrams on page 1298
DocID024597 Rev 3
for details about common assumptions
RM0351