Figure 393. Break Detection In Lin Mode Vs. Framing Error Detection; Usart Synchronous Mode - ST STM32L4x6 Reference Manual

Universal synchronous asynchronous receiver transmitter (USART)
36.5.11

USART synchronous mode

The synchronous mode is selected by writing the CLKEN bit in the USARTx_CR2 register to
1. In synchronous mode, the following bits must be kept cleared:
•
LINEN bit in the USARTx_CR2 register,
•
SCEN, HDSEL and IREN bits in the USARTx_CR3 register.
In this mode, the USART can be used to control bidirectional synchronous serial
communications in master mode. The CK pin is the output of the USART transmitter clock.
No clock pulses are sent to the CK pin during start bit and stop bit. Depending on the state
of the LBCL bit in the USARTx_CR2 register, clock pulses are, or are not, generated during
the last valid data bit (address mark). The CPOL bit in the USARTx_CR2 register is used to
select the clock polarity, and the CPHA bit in the USARTx_CR2 register is used to select the
phase of the external clock (see
During the Idle state, preamble and send break, the external CK clock is not activated.
In synchronous mode the USART transmitter works exactly like in asynchronous mode. But
as CK is synchronized with TX (according to CPOL and CPHA), the data on TX is
synchronous.
In this mode the USART receiver works in a different manner compared to the
asynchronous mode. If RE=1, the data is sampled on CK (rising or falling edge, depending
on CPOL and CPHA), without any oversampling. A setup and a hold time must be
respected (which depends on the baud rate: 1/16 bit duration).
Note: The CK pin works in conjunction with the TX pin. Thus, the clock is provided only if the
transmitter is enabled (TE=1) and data is being transmitted (the data register USARTx_TDR
1204/1693

Figure 393. Break detection in LIN mode vs. Framing error detection

DocID024597 Rev 3
Figure 394, Figure 395 and Figure 396).
RM0351