Figure 455. Swp Bus States; Swpmi_Io (Internal Transceiver) Bypass - ST STM32L4x6 Reference Manual

RM0351
Note: In order to further reduce current consumption once SWPACT bit is cleared, configure the
SWPMI_IO port as output push pull low in GPIO controller (refer to
purpose I/Os
40.3.4

SWPMI_IO (internal transceiver) bypass

A SWPMI_IO (transceiver), compliant with ETSI TS 102 613 technical specification, is
embedded in the microcontroller. Nevertheless, this is possible to bypass it by setting
SWP_TBYP bit in SWPMI_OR register. In this case, the SWPMI_IO is disabled and the
SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are available as alternate
functions on three GPIOs (refer to "Pinouts and pin description" in product datasheet). This
configuration is selected to connect an external transceiver.
40.3.5 SWPMI Bit rate
The bit rate must be set in the SWPMI_BRR register, according to the following formula:
F = F
SWP
Note: The maximum bitrate is 2 Mbit/s.
40.3.6 SWPMI frame handling
The SWP frame is composed of a Start of frame (SOF), a Payload from 1 to 30 bytes, a 16-
bit CRC and an End of frame (EOF) (Refer to
(GPIO)).
/ ((BR[5:0]+1)x4)
SWPCLK
DocID024597 Rev 3
Single Wire Protocol Master Interface (SWPMI)

Figure 455. SWP bus states

Figure 456: SWP frame
Section 7: General-
structure).
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