Figure 354. Setup And Hold Timings - ST STM32L4x6 Reference Manual

RM0351
I2C timings
The timings must be configured in order to guarantee a correct data hold and setup time,
used in master and slave modes. This is done by programming the PRESC[3:0],
SCLDEL[3:0] and SDADEL[3:0] bits in the I2C_TIMINGR register.
•
When the SCL falling edge is internally detected, a delay is inserted before sending
SDA output. This delay is
x t
I2CCLK
T
SDADEL
The total SDA output delay is:
t + {[SDADEL x (PRESC+1) + 1] x t
SYNC1

Figure 354. Setup and hold timings

t
SDADEL
.
impacts the hold time
DocID024597 Rev 3
Inter-integrated circuit (I2C) interface
= SDADEL x t
PRESC
t
HD;DAT.
}
I2CCLK
where
+ t t
I2CCLK PRESC
= (PRESC+1)
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