Table 217. Buffer Modes Selection For Transmission/Reception - ST STM32L4x6 Reference Manual

Single Wire Protocol Master Interface (SWPMI)
Bit 2 RXMODE: Reception buffering mode
Note: This bit cannot be written while SWPACT bit is set.
Bit 1 TXDMA: Transmission DMA enable
Note: TXDMA is automatically cleared if the payload size of the transmitted frame is given as
Bit 0 RXDMA: Reception DMA enable
Buffer mode
RXMODE/TXMODE
RXDMA/TXDMA
1382/1685
This bit is used to choose the reception buffering mode. This bit is relevant only when
TXDMA bit is set (refer to
0: SWPMI is configured in Single software buffer mode for reception
1: SWPMI is configured in Multi software buffer mode for reception.
This bit is used to enable the DMA mode in transmission
0: DMA is disabled for transmission
1: DMA is enabled for transmission
0x00 (in the least significant byte of TDR for the first word of a frame). TXDMA is also
automatically cleared on underrun events (when TXUNRF flag is set in the SWP_ISR
register)
This bit is used to enable the DMA mode in reception
0: DMA is disabled for reception
1: DMA is enabled for reception

Table 217. Buffer modes selection for transmission/reception

No software buffer
Table 217: Buffer modes selection for
Single software buffer
x
0
DocID024597 Rev 3
transmission/reception).
Multi software buffer
0
1
RM0351
1
1