Table 271. Sw-Dp Registers - ST STM32L4x6 Reference Manual

RM0351
IDCODE read or CTRL/STAT read or ABORT write which are accepted even if the write
buffer is full.
•
Because of the asynchronous clock domains SWCLK and HCLK, two extra SWCLK
cycles are needed after a write transaction (after the parity bit) to make the write
effective internally. These cycles should be applied while driving the line low (IDLE
state)
This is particularly important when writing the CTRL/STAT for a power-up request. If the
next transaction (requiring a power-up) occurs immediately, it will fail.
44.8.5 SW-DP registers
Access to these registers are initiated when APnDP=0
A(3:2)
00 Read
00 Write
01 Read/Write
01 Read/Write
10 Read
10 Write
11 Read/Write

Table 271. SW-DP registers

CTRLSEL bit
R/W of SELECT
register
-
-
0
1
-
-
-
DocID024597 Rev 3
Register
The manufacturer code is not set to ST code
IDCODE
0x2BA01477 (identifies the SW-DP)
ABORT
Purpose is to:
– request a system or debug power-up
– configure the transfer operation for AP
DP- accesses
CTRL/STAT
– control the pushed compare and pushed
verify operations.
– read some status flags (overrun, power-
up acknowledges)
Purpose is to configure the physical serial
WIRE
port protocol (like the duration of the
CONTROL
turnaround time)
Enables recovery of the read data from a
READ
corrupted debugger transfer, without
RESEND
repeating the original AP transfer.
The purpose is to select the current access
SELECT
port and the active 4-words register window
This read buffer is useful because AP
accesses are posted (the result of a read AP
request is available on the next AP
READ
transaction).
BUFFER
This read buffer captures data from the AP,
presented as the result of a previous read,
without initiating a new transaction
Debug support (DBG)
Notes
-
1657/1693
1678