Table 250. Response Type And Sdmmc_Respx Registers; Sdmmc Data Timer Register (Sdmmc_Dtimer) - ST STM32L4x6 Reference Manual

RM0351
31 30 29
r r r
15 14 13
r r r
Bits 31:0 CARDSTATUSx: see
The Card Status size is 32 or 127 bits, depending on the response type.
Register
SDMMC_RESP1
SDMMC_RESP2
SDMMC_RESP3
SDMMC_RESP4
The most significant bit of the card status is received first. The SDMMC_RESP4 register
LSB is always 0b.
41.8.7

SDMMC data timer register (SDMMC_DTIMER)

Address offset: 0x24
Reset value: 0x0000 0000
The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods.
A counter loads the value from the SDMMC_DTIMER register, and starts decrementing
when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer
reaches 0 while the DPSM is in either of these states, the timeout status flag is set.
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:0 DATATIME: Data timeout period
Data timeout period expressed in card bus clock periods.
Note: A data transfer must be written to the data timer register and the data length register before
being written to the data control register.
28 27 26 25
r r r r
12 11 10 9
r r r r
Table

Table 250. Response type and SDMMC_RESPx registers

Card Status[31:0]
Unused
Unused
Unused
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
DocID024597 Rev 3
SD/SDIO/MMC card host interface (SDMMC)
24 23 22
CARDSTATUSx[31:16]
r r r
8 7 6
CARDSTATUSx[15:0]
r r r
250.
Short response
24 23 22
DATATIME[31:16]
rw rw rw
8 7 6
DATATIME[15:0]
rw rw rw
21 20 19 18
r r r r
5 4 3 2
r r r r
Long response
Card Status [127:96]
Card Status [95:64]
Card Status [63:32]
Card Status [31:1]0b
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
17 16
r r
1 0
r r
17 16
rw rw
1 0
rw rw
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