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System window watchdog (WWDG)
33.4
WWDG registers
Refer to
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
33.4.1
Control register (WWDG_CR)
Address offset: 0x00
Reset value: 0x0000 007F
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 WDGA: Activation bit
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB)
These bits contain the value of the watchdog counter. It is decremented every (4096 x
WDGTB
2
becomes cleared).
1060/1693
Section 1.1 on page 61
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
0: Watchdog disabled
1: Watchdog enabled
[1:0]
) PCLK cycles. A reset is produced when it rolls over from 0x40 to 0x3F (T6
for a list of abbreviations used in register descriptions.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
WDGA
rs
DocID024597 Rev 3
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
T[6:0]
rw
RM0351
17
16
Res.
Res.
1
0
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