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RM0351
40.6
SWPMI registers
Refer to section 1.1 of the reference manual for a list of abbreviations used in register
descriptions.
The peripheral registers can be accessed by words (32-bit).
40.6.1
SWPMI Configuration/Control register (SWPMI_CR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:11 Reserved, must be kept at reset value
Bit 10 DEACT: Single wire protocol master interface deactivate
Bits 9:6 Reserved, must be kept at reset value
Bit 5 SWPACT: Single wire protocol master interface activate
Bit 4 LPBK: Loopback mode enable
Note: This bit cannot be written while SWPACT bit is set.
Bit 3 TXMODE: Transmission buffering mode
Note: This bit cannot be written while SWPACT bit is set.
27
26
25
Res.
Res.
Res.
11
10
9
Res.
DEACT
Res.
rw
This bit is used to request the SWP DEACTIVATED state. Setting this bit has the same effect
as clearing the SWPACT, except that a possible incoming RESUME by slave will keep the
SWP in the ACTIVATED state.
This bit is used to activate the SWP bus (refer to
activation).
0: SWPMI_IO is pulled down to ground, SWP bus is switched to DEACTIVATED state
1: SWPMI_IO is released, SWP bus is switched to SUSPENDED state
To be able to set SWPACT bit, DEACT bit must be have been cleared previously.
This bit is used to enable the loopback mode
0: Loopback mode is disabled
1: Loopback mode is enabled
This bit is used to choose the transmission buffering mode. This bit is relevant only when
TXDMA bit is set (refer to
0: SWPMI is configured in Single software buffer mode for transmission
1: SWPMI is configured in Multi software buffer mode for transmission.
Single Wire Protocol Master Interface (SWPMI)
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
Table 217: Buffer modes selection for
DocID024597 Rev 3
21
20
19
Res.
Res.
Res.
Res.
5
4
3
SWP
TXMOD
RXMO
LPBK
ACT
E
DE
rw
rw
rw
Section 40.3.2: SWP initialization and
transmission/reception).
18
17
16
Res.
Res.
2
1
0
TXDMA RXDMA
rw
rw
rw
1381/1685
1392
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