Figure 379. Bus Transfer Diagrams For Smbus Slave Receiver (Sbc=1) - ST STM32L4x6 Reference Manual

RM0351 Inter-integrated circuit (I2C) interface

Figure 379. Bus transfer diagrams for SMBus slave receiver (SBC=1)

This section is relevant only when SMBus feature is supported. Please refer to Section 35.3:
I2C implementation.
In addition to I2C master transfer management (refer to Section 35.4.8: I2C master mode)
some additional software flowcharts are provided to support SMBus.
SMBus Master transmitter
When the SMBus master wants to transmit the PEC, the PECBYTE bit must be set and the
number of bytes must be programmed in the NBYTES[7:0] field, before setting the START
bit. In this case the total number of TXIS interrupts will be NBYTES-1. So if the PECBYTE
bit is set when NBYTES=0x1, the content of the I2C_PECR register is automatically
transmitted.
If the SMBus master wants to send a STOP condition after the PEC, automatic end mode
should be selected (AUTOEND=1). In this case, the STOP condition automatically follows
the PEC transmission.
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