Sdmmc Fifo Counter Register (Sdmmc_Fifocnt) - ST STM32L4x6 Reference Manual

RM0351
Bit 8 DATAENDIE: Data end interrupt enable
Bit 7 CMDSENTIE: Command sent interrupt enable
Bit 6 CMDRENDIE: Command response received interrupt enable
Bit 5 RXOVERRIE: Rx FIFO overrun error interrupt enable
Bit 4 TXUNDERRIE: Tx FIFO underrun error interrupt enable
Bit 3 DTIMEOUTIE: Data timeout interrupt enable
Bit 2 CTIMEOUTIE: Command timeout interrupt enable
Bit 1 DCRCFAILIE: Data CRC fail interrupt enable
Bit 0 CCRCFAILIE: Command CRC fail interrupt enable
41.8.14

SDMMC FIFO counter register (SDMMC_FIFOCNT)

Address offset: 0x48
Reset value: 0x0000 0000
The SDMMC_FIFOCNT register contains the remaining number of words to be written to or
read from the FIFO. The FIFO counter loads the value from the data length register (see
SDMMC_DLEN) when the data transfer enable bit, DTEN, is set in the data control register
(SDMMC_DCTRL register) and the DPSM is at the Idle state. If the data length is not word-
aligned (multiple of 4), the remaining 1 to 3 bytes are regarded as a word.
Set and cleared by software to enable/disable interrupt caused by data end.
0: Data end interrupt disabled
1: Data end interrupt enabled
Set and cleared by software to enable/disable interrupt caused by sending command.
0: Command sent interrupt disabled
1: Command sent interrupt enabled
Set and cleared by software to enable/disable interrupt caused by receiving command
response.
0: Command response received interrupt disabled
1: command Response Received interrupt enabled
Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error.
0: Rx FIFO overrun error interrupt disabled
1: Rx FIFO overrun error interrupt enabled
Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error.
0: Tx FIFO underrun error interrupt disabled
1: Tx FIFO underrun error interrupt enabled
Set and cleared by software to enable/disable interrupt caused by data timeout.
0: Data timeout interrupt disabled
1: Data timeout interrupt enabled
Set and cleared by software to enable/disable interrupt caused by command timeout.
0: Command timeout interrupt disabled
1: Command timeout interrupt enabled
Set and cleared by software to enable/disable interrupt caused by data CRC failure.
0: Data CRC fail interrupt disabled
1: Data CRC fail interrupt enabled
Set and cleared by software to enable/disable interrupt caused by command CRC failure.
0: Command CRC fail interrupt disabled
1: Command CRC fail interrupt enabled
SD/SDIO/MMC card host interface (SDMMC)
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