Table 279. Important Tpiu Registers - ST STM32L4x6 Reference Manual

Debug support (DBG)
44.17.9 TPIU registers
The TPIU APB registers can be read and written only if the bit TRCENA of the Debug
Exception and Monitor Control Register (DEMCR) is set. Otherwise, the registers are read
as zero (the output of this bit enables the PCLK of the TPIU).
Address
0xE0040004 Current port size
0xE00400F0
0xE0040304
0xE0040300
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Table 279. Important TPIU registers

Register
Allows the trace port size to be selected:
Bit 0: Port size = 1
Bit 1: Port size = 2
Bit 2: Port size = 3, not supported
Bit 3: Port Size = 4
Only 1 bit must be set. By default, the port size is one bit.
(0x00000001)
Allows the Trace Port Protocol to be selected:
Bit1:0 =
Selected pin
00: Synchronous Trace Port Mode
protocol
01: Serial Wire Output - manchester (default value)
10: Serial Wire Output - NRZ
11: reserved
Bit 31-9 = always '0'
Bit 8 = TrigIn = always '1' to indicate that triggers are indicated
Bit 7-4 = always 0
Bit 3-2 = always 0
Bit 1 = EnFCont. In Synchronous Trace mode
(Select_Pin_Protocol register bit1:0 = 00), this bit is forced to
'1': the formatter is automatically enabled in continuous mode.
Formatter and
In asynchronous mode (Select_Pin_Protocol register bit1:0 <>
flush control
00), this bit can be written to activate or not the formatter.
Bit 0 = always '0'
The resulting default value is 0x102
Note: In synchronous mode, because the TRACECTL pin is not
mapped outside the chip, the formatter is always enabled in
continuous mode; this way the formatter inserts some control
packets to identify the source of the trace packets).
Formatter and
Not used in Cortex
flush status
DocID024597 Rev 3
Description
®
-M4, always read as 0x00000008
RM0351